Merge e36dd0b445 into cc1de9f039

Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>

README.md

@@ -3,9 +3,10 @@ meta-sunxi
 
 Official sunxi OpenEmbedded layer for Allwinner-based boards.
 
-This layer depends on the additional layer:
+This layer depends on the additional layers:
 
-meta-openembedded: git://git.openembedded.org/meta-openembedded
+* [meta-openembedded/meta-oe](http://git.openembedded.org/meta-openembedded/tree/meta-oe)
+* [meta-arm](https://git.yoctoproject.org/meta-arm)
 
 Tested with core-image-base.
 
@@ -14,30 +15,46 @@ Maintainers:
 * Nicolas Aguirre <aguirre.nicolas@gmail.com>
 * Enrico Butera <ebutera@users.sourceforge.net>
 * Sergey Lapin <slapin@ossfans.org>
+* Marek Belisko <marek.belisko@gmail.com>
+
+Community
+===========
+
+You can reach community + ask your question on gitter: https://matrix.to/#/#meta-sunxi:gitter.im
 
 Kernel / U-Boot Version
 ===========
 Most Allwinner devices and hardware are supported in mainline kernel and U-Boot, so this layer builds mainline by default.
+
+Legacy sunxi Kernel / U-Boot
+-----------
+
 There is a custom U-Boot and Kernel version for sunxi devices which includes some special drivers not mainlined.
-These versions are rather old (3.4 for kernel and 2014.04 for U-Boot), but may support more functions and devices than current mainline 
+These versions are rather old (3.4 for kernel and 2014.04 for U-Boot), but may support more functions and devices than current mainline.
 
 If you want to switch back to sunxi versions for some reasons (no device tree available, unsupported hardware), either:
 - change the file conf/machine/include/sunxi.inc to include the following block
 - edit your conf/local.conf to add the following block
 
-	PREFERRED_PROVIDER_u-boot="u-boot-sunxi"
-	PREFERRED_PROVIDER_virtual/bootloader="u-boot-sunxi"
-	PREFERRED_PROVIDER_virtual/kernel="linux-sunxi"
+		PREFERRED_PROVIDER_u-boot="u-boot-sunxi"
+		PREFERRED_PROVIDER_virtual/bootloader="u-boot-sunxi"
+		PREFERRED_PROVIDER_virtual/kernel="linux-sunxi"
+		KERNEL_DEVICETREE = ""
 
 If you already have built the mainline versions it might be necessary to reset the build directories with:
 
-	bitbake -c clean linux
-	bitbake -c clean u-boot
+	bitbake -c clean virtual/kernel virtual/bootloader
 
-Also, older kernel versions such as this don't build successfully with any gcc version 5.0 or newer. Since gcc-5.2 is the current
-default compiler on master, if you wish to build this kernel with master you'll need to add the following to your conf/local.conf:
+Mainline Kernel / U-Boot
+-----------
 
-	GCCVERSION = "4.9%"
+For mainline kernel we have now support for latest LTS and stable.
+By default we use latest LTS. If you would like to change version please update ```PREFERRED_VERSION_linux-mainline``` in:
+* [conf/machine/include/sunxi.inc](https://github.com/linux-sunxi/meta-sunxi/blob/fa0846c0eb23e3424b89acb4d5a327e921f73497/conf/machine/include/sunxi.inc#L16)
+
+When using mainline kernel ≥ 5.2 it is now possible to use the mainline graphics drivers *lima* and *panfrost*, instead of the *mali* driver provided by ARM. To enable open source mainline graphics support add the following line in your `local.conf`:
+
+    MACHINEOVERRIDES .= ":use-mailine-graphics"
 
 Performance
 ===========

classes/sdcard_image-sunxi.bbclass

@@ -1,114 +0,0 @@
-inherit image_types
-
-#
-# Create an image that can by written onto a SD card using dd.
-# Originally written for rasberrypi adapt for the needs of allwinner sunxi based boards
-#
-# The disk layout used is:
-#
-#    0                      -> 8*1024                           - reserverd
-#    8*1024                 -> 32*1024                          - 
-#    32*1024                -> 2048*1024                        - 
-#    2048*1024              -> BOOT_SPACE                       - bootloader and kernel
-#
-#
-
-# This image depends on the rootfs image
-IMAGE_TYPEDEP_sunxi-sdimg = "${SDIMG_ROOTFS_TYPE}"
-
-# Boot partition volume id
-BOOTDD_VOLUME_ID ?= "${MACHINE}"
-
-# Boot partition size [in KiB]
-BOOT_SPACE ?= "20480"
-
-# First partition begin at sector 2048 : 2048*1024 = 2097152
-IMAGE_ROOTFS_ALIGNMENT = "2048"
-
-# Use an uncompressed ext3 by default as rootfs
-SDIMG_ROOTFS_TYPE ?= "ext4"
-SDIMG_ROOTFS = "${DEPLOY_DIR_IMAGE}/${IMAGE_NAME}.rootfs.${SDIMG_ROOTFS_TYPE}"
-
-IMAGE_DEPENDS_sunxi-sdimg += " \
-			parted-native \
-			mtools-native \
-			dosfstools-native \
-			virtual/kernel \
-			virtual/bootloader \
-			"
-
-rootfs[depends] += "virtual/kernel:do_deploy"
-
-# SD card image name
-SDIMG = "${DEPLOY_DIR_IMAGE}/${IMAGE_NAME}.rootfs.sunxi-sdimg"
-
-IMAGEDATESTAMP = "${@time.strftime('%Y.%m.%d',time.gmtime())}"
-
-IMAGE_CMD_sunxi-sdimg () {
-
-	# Align partitions
-	BOOT_SPACE_ALIGNED=$(expr ${BOOT_SPACE} + ${IMAGE_ROOTFS_ALIGNMENT} - 1)
-	BOOT_SPACE_ALIGNED=$(expr ${BOOT_SPACE_ALIGNED} - ${BOOT_SPACE_ALIGNED} % ${IMAGE_ROOTFS_ALIGNMENT})
-	SDIMG_SIZE=$(expr ${IMAGE_ROOTFS_ALIGNMENT} + ${BOOT_SPACE_ALIGNED} + $ROOTFS_SIZE + ${IMAGE_ROOTFS_ALIGNMENT})
-
-	# Initialize sdcard image file
-	dd if=/dev/zero of=${SDIMG} bs=1 count=0 seek=$(expr 1024 \* ${SDIMG_SIZE})
-
-	# Create partition table
-	parted -s ${SDIMG} mklabel msdos
-	# Create boot partition and mark it as bootable
-	parted -s ${SDIMG} unit KiB mkpart primary fat32 ${IMAGE_ROOTFS_ALIGNMENT} $(expr ${BOOT_SPACE_ALIGNED} \+ ${IMAGE_ROOTFS_ALIGNMENT})
-	parted -s ${SDIMG} set 1 boot on
-	# Create rootfs partition
-	parted -s ${SDIMG} unit KiB mkpart primary ext2 $(expr ${BOOT_SPACE_ALIGNED} \+ ${IMAGE_ROOTFS_ALIGNMENT}) $(expr ${BOOT_SPACE_ALIGNED} \+ ${IMAGE_ROOTFS_ALIGNMENT} \+ ${ROOTFS_SIZE})
-	parted ${SDIMG} print
-
-	# Create a vfat image with boot files
-	BOOT_BLOCKS=$(LC_ALL=C parted -s ${SDIMG} unit b print | awk '/ 1 / { print substr($4, 1, length($4 -1)) / 512 /2 }')
-	rm -f ${WORKDIR}/boot.img
-	mkfs.vfat -n "${BOOTDD_VOLUME_ID}" -S 512 -C ${WORKDIR}/boot.img $BOOT_BLOCKS
-
-	mcopy -i ${WORKDIR}/boot.img -s ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${MACHINE}.bin ::uImage
-
-	# Copy device tree file
-	if test -n "${KERNEL_DEVICETREE}"; then
-		for DTS_FILE in ${KERNEL_DEVICETREE}; do
-			DTS_BASE_NAME=`basename ${DTS_FILE} | awk -F "." '{print $1}'`
-			if [ -e "${KERNEL_IMAGETYPE}-${DTS_BASE_NAME}.dtb" ]; then
-				kernel_bin="`readlink ${KERNEL_IMAGETYPE}-${MACHINE}.bin`"
-				kernel_bin_for_dtb="`readlink ${KERNEL_IMAGETYPE}-${DTS_BASE_NAME}.dtb | sed "s,$DTS_BASE_NAME,${MACHINE},g;s,\.dtb$,.bin,g"`"
-				if [ $kernel_bin = $kernel_bin_for_dtb ]; then
-					mcopy -i ${WORKDIR}/boot.img -s ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTS_BASE_NAME}.dtb ::/${DTS_BASE_NAME}.dtb
-				fi
-			fi
-		done
-	fi
-
-	if [ -e "${DEPLOY_DIR_IMAGE}/fex.bin" ]
-	then
-		mcopy -i ${WORKDIR}/boot.img -s ${DEPLOY_DIR_IMAGE}/fex.bin ::script.bin
-	fi
-	if [ -e "${DEPLOY_DIR_IMAGE}/boot.scr" ]
-	then
-		mcopy -i ${WORKDIR}/boot.img -s ${DEPLOY_DIR_IMAGE}/boot.scr ::boot.scr
-	fi
-
-
-	# Add stamp file
-	echo "${IMAGE_NAME}-${IMAGEDATESTAMP}" > ${WORKDIR}/image-version-info
-	mcopy -i ${WORKDIR}/boot.img -v ${WORKDIR}//image-version-info ::
-
-	# Burn Partitions
-	dd if=${WORKDIR}/boot.img of=${SDIMG} conv=notrunc seek=1 bs=$(expr ${IMAGE_ROOTFS_ALIGNMENT} \* 1024) && sync && sync
-	# If SDIMG_ROOTFS_TYPE is a .xz file use xzcat
-	if echo "${SDIMG_ROOTFS_TYPE}" | egrep -q "*\.xz"
-	then
-		xzcat ${SDIMG_ROOTFS} | dd of=${SDIMG} conv=notrunc seek=1 bs=$(expr 1024 \* ${BOOT_SPACE_ALIGNED} + ${IMAGE_ROOTFS_ALIGNMENT} \* 1024) && sync && sync
-	else
-		dd if=${SDIMG_ROOTFS} of=${SDIMG} conv=notrunc seek=1 bs=$(expr 1024 \* ${BOOT_SPACE_ALIGNED} + ${IMAGE_ROOTFS_ALIGNMENT} \* 1024) && sync && sync
-	fi
-
-	#write u-boot and spl at the beginint of sdcard in one shot
-	dd if=${DEPLOY_DIR_IMAGE}/u-boot-sunxi-with-spl.bin of=${SDIMG} bs=1024 seek=8 conv=notrunc
-
-}

conf/layer.conf

@@ -4,6 +4,14 @@ BBPATH .= ":${LAYERDIR}"
 # We have a recipes directory, add to BBFILES
 BBFILES += "${LAYERDIR}/recipes*/*/*.bb ${LAYERDIR}/recipes*/*/*.bbappend"
 
-BBFILE_COLLECTIONS += "meta-sunxi"
-BBFILE_PATTERN_meta-sunxi := "^${LAYERDIR}/"
-BBFILE_PRIORITY_meta-sunxi = "10"
+BBFILE_COLLECTIONS += "sunxi"
+BBFILE_PATTERN_sunxi := "^${LAYERDIR}/"
+BBFILE_PRIORITY_sunxi = "10"
+
+# This should only be incremented on significant changes that will
+# cause compatibility issues with other layers
+LAYERVERSION_sunxi = "1"
+
+LAYERDEPENDS_sunxi = "core meta-python meta-arm"
+
+LAYERSERIES_COMPAT_sunxi = "honister kirkstone langdale mickledore nanbield"

conf/machine/bananapi-m2-zero.conf

@@ -0,0 +1,10 @@
+#@TYPE: Machine
+#@NAME: bananapi-m2-zero
+#@DESCRIPTION: Machine configuration for the Banana Pi M2 Zero, base on Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+require conf/machine/include/hardware/ap6212a.inc
+
+KERNEL_DEVICETREE = "sun8i-h2-plus-bananapi-m2-zero.dtb"
+UBOOT_MACHINE = "bananapi_m2_zero_defconfig"
+

conf/machine/bananapi-m2m.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: bananapi-m2m
+#@DESCRIPTION: Machine configuration for the Banana Pi M2M, base on Allwinner H8 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-r16-bananapi-m2m.dtb"
+UBOOT_MACHINE = "Bananapi_m2m_defconfig"
+

conf/machine/bananapi-m2plus.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: bananapi-m2plus
+#@DESCRIPTION: Machine configuration for the Banana Pi M2+, base on Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-bananapi-m2-plus.dtb"
+UBOOT_MACHINE = "bananapi_m2_plus_h3_defconfig"
+

conf/machine/bananapi-m64.conf

@@ -0,0 +1,8 @@
+#@TYPE: Machine
+#@NAME: pine64-plus
+#@DESCRIPTION: Machine configuration for the pine64-plus, based on Allwinner A64 CPU
+
+require conf/machine/include/sun50i.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-a64-bananapi-m64.dtb"
+UBOOT_MACHINE = "bananapi_m64_defconfig"

conf/machine/include/hardware/ap6212a.inc

@@ -0,0 +1,5 @@
+# Include for boards with AMPAK 6212A Wifi / Bluetooth module
+# https://linux-sunxi.org/Wifi#Ampak
+
+MACHINE_EXTRA_RRECOMMENDS:append = " kernel-module-brcmfmac"
+MACHINE_EXTRA_RDEPENDS:append = " linux-firmware-bcm43430"

conf/machine/include/sun4i.inc

@@ -1,5 +1,5 @@
 require conf/machine/include/sunxi.inc
 require conf/machine/include/sunxi-mali.inc
-require conf/machine/include/tune-cortexa8.inc
+require conf/machine/include/arm/armv7a/tune-cortexa8.inc
 
 SOC_FAMILY = "sun4i"

conf/machine/include/sun50i-h6.inc

@@ -0,0 +1,8 @@
+require conf/machine/include/sunxi64.inc
+
+DEFAULTTUNE ?= "cortexa53-crypto"
+require conf/machine/include/arm/armv8a/tune-cortexa53.inc
+
+MACHINEOVERRIDES =. "sun50i:"
+
+SOC_FAMILY = "sun50i-h6"

conf/machine/include/sun50i-h616.inc

@@ -0,0 +1,8 @@
+require conf/machine/include/sunxi64.inc
+
+DEFAULTTUNE ?= "cortexa53-crypto"
+require conf/machine/include/arm/armv8a/tune-cortexa53.inc
+
+MACHINEOVERRIDES =. "sun50i:"
+
+SOC_FAMILY = "sun50i-h616"

conf/machine/include/sun50i.inc

@@ -0,0 +1,6 @@
+require conf/machine/include/sunxi64.inc
+
+DEFAULTTUNE ?= "cortexa53-crypto"
+require conf/machine/include/arm/armv8a/tune-cortexa53.inc
+
+SOC_FAMILY = "sun50i"

conf/machine/include/sun5i.inc

@@ -1,5 +1,5 @@
 require conf/machine/include/sunxi.inc
 require conf/machine/include/sunxi-mali.inc
-require conf/machine/include/tune-cortexa8.inc
+require conf/machine/include/arm/armv7a/tune-cortexa8.inc
 
 SOC_FAMILY = "sun5i"

conf/machine/include/sun7i.inc

@@ -1,5 +1,5 @@
 require conf/machine/include/sunxi.inc
 require conf/machine/include/sunxi-mali.inc
-require conf/machine/include/tune-cortexa7.inc
+require conf/machine/include/arm/armv7a/tune-cortexa7.inc
 
 SOC_FAMILY = "sun7i"

conf/machine/include/sun8i.inc

@@ -0,0 +1,5 @@
+require conf/machine/include/sunxi.inc
+require conf/machine/include/sunxi-mali.inc
+require conf/machine/include/arm/armv7a/tune-cortexa7.inc
+
+SOC_FAMILY = "sun8i"

conf/machine/include/sunxi-mali-driver.inc

@@ -0,0 +1,15 @@
+PREFERRED_PROVIDER_virtual/mesa ?= "mesa-gl"
+PREFERRED_PROVIDER_virtual/libgl ?= "mesa-gl"
+PREFERRED_PROVIDER_virtual/libgles1 ?= "sunxi-mali"
+PREFERRED_PROVIDER_virtual/libgles2 ?= "sunxi-mali"
+PREFERRED_PROVIDER_virtual/egl ?= "sunxi-mali"
+
+PACKAGECONFIG:remove:pn-xserver-xorg = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'glamor', '', d)}"
+
+XSERVER += "sunxi-mali \
+            sunxi-mali-dev"
+
+MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS += "\
+ kernel-module-mali \
+ kernel-module-mali-drm \
+  "

conf/machine/include/sunxi-mali.inc

@@ -1,13 +1,5 @@
-PREFERRED_PROVIDER_virtual/mesa ?= "mesa-gl"
-PREFERRED_PROVIDER_virtual/libgl ?= "mesa-gl"
-PREFERRED_PROVIDER_virtual/libgles1 ?= "sunxi-mali"
-PREFERRED_PROVIDER_virtual/libgles2 ?= "sunxi-mali"
-PREFERRED_PROVIDER_virtual/egl ?= "sunxi-mali"
-
-XSERVER += "sunxi-mali \
-            sunxi-mali-dev"
-
-MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS += "\
- kernel-module-mali \
- kernel-module-mali-drm \
-  "
+# The "sunxi-mailine-graphics-drivers.inc" doesn't exist, but it can be created
+# in the future if needed.  Using include directive ensures build doesn't fail
+# if .inc file doesn't exist:
+# https://www.yoctoproject.org/pipermail/yocto/2019-August/046484.html
+include ${@'sunxi-mali-driver.inc' if 'use-mailine-graphics' not in d.getVar("MACHINEOVERRIDES").split(":") else 'sunxi-mailine-graphics-drivers.inc' }

conf/machine/include/sunxi.inc

@@ -1,32 +1,47 @@
 SOC_FAMILY ??= ""
 include conf/machine/include/soc-family.inc
 
+MACHINEOVERRIDES =. "sunxi:"
+
 # Sub-architecture support
 MACHINE_SOCARCH_SUFFIX ?= ""
 MACHINE_SOCARCH_SUFFIX_sun4i = "-sun4i"
 
 PREFERRED_PROVIDER_virtual/xserver = "xserver-xorg"
 XSERVER = "xserver-xorg \
-           xf86-video-fbturbo \
            xf86-input-evdev \
            xf86-input-mouse \
            xf86-input-keyboard"
 
-PREFERRED_PROVIDER_virtual/kernel ?= "linux"
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-mainline"
+PREFERRED_VERSION_linux-mainline ?= "6.5.%"
 PREFERRED_PROVIDER_u-boot ?= "u-boot"
 PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
 
 KERNEL_IMAGETYPE ?= "uImage"
 
-IMAGE_CLASSES += "sdcard_image-sunxi"
-IMAGE_FSTYPES += "ext3 tar.gz sunxi-sdimg"
+IMAGE_FSTYPES += "ext3 tar.gz wic.gz wic.bmap"
 
 MACHINE_EXTRA_RRECOMMENDS = "kernel-modules"
 
 UBOOT_LOCALVERSION = "-g${@d.getVar('SRCPV', True).partition('+')[2][0:7]}"
 
 UBOOT_ENTRYPOINT ?= "0x40008000"
-UBOOT_LOADADDRESS ?= "0x400080OB00"
 
-SERIAL_CONSOLE ?= "115200 ttyS0"
+SPL_BINARY ?= "u-boot-sunxi-with-spl.bin"
+
+SERIAL_CONSOLES ?= "115200;ttyS0"
 MACHINE_FEATURES ?= "alsa apm keyboard rtc serial screen usbgadget usbhost vfat"
+
+# Mimic the sdcard_image-sunxi.bbclass
+# image-version-info file was also generated and installed to boot partition,
+# but it is missing here - can be added somehow (how?) if required
+SUNXI_FEX_FILE ?= " "
+SUNXI_BOOT_SPACE ?= "40"
+IMAGE_BOOT_FILES ?= "${KERNEL_IMAGETYPE} boot.scr"
+# ship fex file for sunxi kernel, devicetree file for mainline kernel
+IMAGE_BOOT_FILES += "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/kernel', 'linux-sunxi', '${SUNXI_FEX_FILE}', '${KERNEL_DEVICETREE}', d)}"
+WKS_FILES ?= "sunxi-sdcard-image.wks.in"
+WKS_FILE_DEPENDS ?= "virtual/kernel u-boot"
+# in case of sunxi kernel, sunxi-board-fex must be built prior wic image assembly
+WKS_FILE_DEPENDS += " ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/kernel', 'linux-sunxi', 'sunxi-board-fex', '', d)}"

conf/machine/include/sunxi64.inc

@@ -0,0 +1,52 @@
+SOC_FAMILY ??= ""
+include conf/machine/include/soc-family.inc
+
+MACHINEOVERRIDES =. "sunxi:sunxi64:"
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-mainline"
+PREFERRED_VERSION_linux-mainline ?= "6.1.%"
+PREFERRED_PROVIDER_u-boot ?= "u-boot"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
+
+KERNEL_IMAGETYPE ?= "Image"
+
+IMAGE_FSTYPES += "ext4 tar.gz wic.gz wic.bmap"
+
+MACHINE_EXTRA_RRECOMMENDS = "kernel-modules"
+
+UBOOT_LOCALVERSION = "-g${@d.getVar('SRCPV', True).partition('+')[2][0:7]}"
+
+UBOOT_ENTRYPOINT ?= "0x40008000"
+UBOOT_LOADADDRESS ?= "0x400080OB00"
+
+#UBOOT_BINARY ?= "u-boot.itb"
+SPL_BINARY ?= "u-boot-sunxi-with-spl.bin"
+
+SERIAL_CONSOLES ?= "115200;ttyS0"
+MACHINE_FEATURES ?= "alsa apm keyboard rtc serial screen usbgadget usbhost vfat"
+
+# arm64 dbts are under <vendor>/dts but is deployed under DEPLOYDIR 
+do_fix_device_tree_location() {
+
+    for kdt in ${KERNEL_DEVICETREE}
+    do
+        local dbt_dir=$(dirname ${kdt})
+        if [ "." != "${dbt_dir}" ] ; then
+            local dbt=$(basename ${kdt})
+            local dst=${DEPLOY_DIR_IMAGE}/${dbt_dir}/${dbt}
+            if [ ! -f ${dst} ] ; then
+                mkdir -p ${DEPLOY_DIR_IMAGE}/$dbt_dir
+                ln -s ${DEPLOY_DIR_IMAGE}/${dbt} ${dst}
+            fi
+        fi
+    done
+}
+
+
+addtask do_fix_device_tree_location after do_write_wks_template before do_image_wic
+
+SUNXI_BOOT_SPACE ?= "40"
+IMAGE_BOOT_FILES ?= "${KERNEL_IMAGETYPE} boot.scr ${KERNEL_DEVICETREE}"
+
+WKS_FILES ?= "sunxi-sdcard-image.wks.in"
+WKS_FILE_DEPENDS ?= "virtual/kernel u-boot"

conf/machine/lamobo-r1.conf

@@ -0,0 +1,10 @@
+#@TYPE: Machine
+#@NAME: Lamobo R1
+#@DESCRIPTION: Machine configuration for the lamobo r1, based on allwinner A20 CPU http://bananapi.org/
+
+require conf/machine/include/sun7i.inc
+
+MACHINE_EXTRA_RRECOMMENDS = " kernel-modules kernel-devicetree"
+KERNEL_DEVICETREE = "sun7i-a20-lamobo-r1.dtb"
+UBOOT_MACHINE = "Lamobo_R1_config"
+SUNXI_FEX_FILE = "sys_config/a20/lamobo-r1.fex"

conf/machine/licheepi-zero.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: licheepi-zero
+#@DESCRIPTION: Machine configuration for the licheepi-zero, based on allwinner V3s CPU
+
+require conf/machine/include/sun8i.inc
+
+
+UBOOT_MACHINE = "LicheePi_Zero_defconfig"
+KERNEL_DEVICETREE = "sun8i-v3s-licheepi-zero.dtb"

conf/machine/marsboard-a10.conf

@@ -0,0 +1,10 @@
+#@TYPE: Machine
+#@NAME: HAOYU Electronics MarsBoard A10
+#@DESCRIPTION: Machine configuration for the HAOYU Electronics MarsBoard A10, based on Allwinner A10 CPU
+#https://linux-sunxi.org/MarsBoard_A10
+
+require conf/machine/include/sun4i.inc
+
+KERNEL_DEVICETREE = "sun4i-a10-marsboard.dtb"
+UBOOT_MACHINE = "Marsboard_A10_config"
+SUNXI_FEX_FILE = "sys_config/a10/marsboard_a10.fex"

conf/machine/nanopi-m1-plus.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: nanopi M1 Plus
+#@DESCRIPTION: Machine configuration for the FriendlyARM NanoPi Neo, based on the Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-nanopi-m1-plus.dtb"
+UBOOT_MACHINE = "nanopi_m1_plus_defconfig"
+

conf/machine/nanopi-m1.conf

@@ -0,0 +1,8 @@
+#@TYPE: Machine
+#@NAME: NanoPi M1
+#@DESCRIPTION: Machine configuration for the FriendlyARM NanoPi Neo, based on #the Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-nanopi-m1.dtb"
+UBOOT_MACHINE = "nanopi_m1_defconfig"

conf/machine/nanopi-neo-air.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: nanopi-neo-air
+#@DESCRIPTION: Machine configuration for the FriendlyARM NanoPi Neo Air, based
+# on the Allwinner H3 CPU.
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-nanopi-neo-air.dtb"
+UBOOT_MACHINE = "nanopi_neo_air_defconfig"

conf/machine/nanopi-neo-plus2.conf

@@ -0,0 +1,10 @@
+#@TYPE: Machine
+#@NAME: nanopi-neo-plus2
+#@DESCRIPTION: Machine configuration for the FriendlyARM NanoPi Neo Plus2, based
+# on the Allwinner H5 SoC.
+
+require conf/machine/include/sun50i.inc
+require conf/machine/include/hardware/ap6212a.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-h5-nanopi-neo-plus2.dtb"
+UBOOT_MACHINE = "nanopi_neo_plus2_defconfig"

conf/machine/nanopi-neo.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: nanopi-neo
+#@DESCRIPTION: Machine configuration for the FriendlyARM NanoPi Neo, based on the Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-nanopi-neo.dtb"
+UBOOT_MACHINE = "nanopi_neo_defconfig"
+

conf/machine/nanopi-neo2.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: nanopi-neo2
+#@DESCRIPTION: Machine configuration for the FriendlyARM NanoPi Neo 2, based on
+# the Allwinner H5 SoC.
+
+require conf/machine/include/sun50i.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-h5-nanopi-neo2.dtb"
+UBOOT_MACHINE = "nanopi_neo2_defconfig"

conf/machine/nanopi-r1.conf

@@ -0,0 +1,8 @@
+#@TYPE: Machine
+#@NAME: NanoPi R1
+#@DESCRIPTION: Machine configuration for the FriendlyARM NanoPi R1, based on #the Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-nanopi-r1.dtb"
+UBOOT_MACHINE = "nanopi_r1_defconfig"

conf/machine/olinuxino-a20lime2-emmc.conf

@@ -0,0 +1,10 @@
+#@TYPE: Machine
+#@NAME: Olimex A20-OLinuXino Lime2 Board with 4GB eMMC
+#@DESCRIPTION: Machine configuration for the Olimex A20-OLinuXino Lime2 Board with 4GB eMMC, based on Allwinner A20 CPU
+#https://github.com/OLIMEX/OLINUXINO
+
+require conf/machine/include/sun7i.inc
+
+KERNEL_DEVICETREE = "sun7i-a20-olinuxino-lime2-emmc.dtb"
+UBOOT_MACHINE = "A20-OLinuXino-Lime2-eMMC_config"
+SUNXI_FEX_FILE = "sys_config/a20/a20-olinuxino_lime2.fex"

conf/machine/olinuxino-a20som.conf

@@ -5,5 +5,6 @@
 
 require conf/machine/include/sun7i.inc
 
-UBOOT_MACHINE = "Olimex_A20-SOM_config"
-SUNXI_FEX_FILE = "sys_config/a20/olimex_a20_som.fex"
+KERNEL_DEVICETREE = "sun7i-a20-olimex-som-evb.dtb"
+UBOOT_MACHINE = "A20-Olimex-SOM-EVB_config"
+SUNXI_FEX_FILE = "sys_config/a20/olimex_a20_som.fex"

conf/machine/olinuxino-a64.conf

@@ -0,0 +1,13 @@
+#@TYPE: Machine
+#@NAME: Olimex A64-OLinuXino Board
+#@DESCRIPTION: Machine configuration for the Olimex A64-OLinuXino Board, based on Allwinner A64 CPU
+#https://github.com/OLIMEX/OLINUXINO
+
+require conf/machine/include/sun50i.inc
+
+PREFFERED_VERSION_u-boot = "v2018.09%"
+
+MACHINE_EXTRA_RRECOMMENDS += " linux-firmware-rtl8723"
+
+KERNEL_DEVICETREE = "allwinner/sun50i-a64-olinuxino.dtb"
+UBOOT_MACHINE = "a64-olinuxino_defconfig"

conf/machine/orange-pi-3lts.conf

@@ -0,0 +1,15 @@
+#@TYPE: Machine
+#@NAME: orange-pi-3lts
+#@DESCRIPTION: Machine configuration for the Orange Pi 3 LTS , based on Allwinner H6 CPU
+
+require conf/machine/include/sun50i-h6.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-h6-orangepi-3-lts.dtb"
+UBOOT_MACHINE = "orangepi_3_lts_defconfig"
+
+SPL_BINARY = "u-boot-sunxi-with-spl.bin"
+
+# as for now neither graphics nor audio is supported
+MACHINE_FEATURES:remove = "alsa x11 bluetooth wifi"
+#MACHINE_FEATURES:append = "bluetooth wifi"
+

conf/machine/orange-pi-lite.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-lite
+#@DESCRIPTION: Machine configuration for the orange-pi-lite, based on Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-orangepi-lite.dtb"
+UBOOT_MACHINE = "orangepi_lite_defconfig"
+

conf/machine/orange-pi-one-plus.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-one-plus
+#@DESCRIPTION: Machine configuration for the Orange Pi One Plus, based on Allwinner H6 CPU
+
+
+require conf/machine/include/sun50i-h6.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-h6-orangepi-one-plus.dtb"
+UBOOT_MACHINE = "orangepi_one_plus_defconfig"

conf/machine/orange-pi-one.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-one
+#@DESCRIPTION: Machine configuration for the orange-pi-one, base on allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-orangepi-one.dtb"
+UBOOT_MACHINE = "orangepi_one_defconfig"
+

conf/machine/orange-pi-pc-plus.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-pc-plus
+#@DESCRIPTION: Machine configuration for the orange-pi-pc-plus, base on allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-orangepi-pc-plus.dtb"
+UBOOT_MACHINE = "orangepi_pc_plus_defconfig"
+

conf/machine/orange-pi-pc.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-one
+#@DESCRIPTION: Machine configuration for the orange-pi-one, base on allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-orangepi-pc.dtb"
+UBOOT_MACHINE = "orangepi_pc_defconfig"
+

conf/machine/orange-pi-pc2.conf

@@ -0,0 +1,8 @@
+#@TYPE: Machine
+#@NAME: orangepi-pc2
+#@DESCRIPTION: Machine configuration for the orangepi-pc2, based on Allwinner A64 CPU
+
+require conf/machine/include/sun50i.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-h5-orangepi-pc2.dtb"
+UBOOT_MACHINE = "orangepi_pc2_defconfig"

conf/machine/orange-pi-r1.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-r1
+#@DESCRIPTION: Machine configuration for the orange-pi-r1, base on allwinner H2+ CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h2-plus-orangepi-r1.dtb"
+UBOOT_MACHINE = "orangepi_r1_defconfig"
+

conf/machine/orange-pi-zero-plus2-h3.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-zero-plus2-h3
+#@DESCRIPTION: Machine configuration for the orange-pi-zero-plus2, based on Allwinner H3 CPU
+
+require conf/machine/include/sun8i.inc
+require conf/machine/include/hardware/ap6212a.inc
+
+KERNEL_DEVICETREE = "sun8i-h3-orangepi-zero-plus2.dtb"
+UBOOT_MACHINE = "orangepi_zero_plus2_h3_defconfig"

conf/machine/orange-pi-zero-plus2.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-zero-plus2
+#@DESCRIPTION: Machine configuration for the orange-pi-zero-plus2, base on Allwinner H5 CPU
+
+require conf/machine/include/sun50i.inc
+require conf/machine/include/hardware/ap6212a.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-h5-orangepi-zero-plus2.dtb"
+UBOOT_MACHINE = "orangepi_zero_plus2_defconfig"

conf/machine/orange-pi-zero.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: orange-pi-zero
+#@DESCRIPTION: Machine configuration for the orange-pi-zero, based on Allwinner H2 CPU
+
+require conf/machine/include/sun8i.inc
+
+KERNEL_DEVICETREE = "sun8i-h2-plus-orangepi-zero.dtb"
+UBOOT_MACHINE = "orangepi_zero_defconfig"
+

conf/machine/orange-pi-zero2.conf

@@ -0,0 +1,16 @@
+#@TYPE: Machine
+#@NAME: orange-pi-zero-2
+#@DESCRIPTION: Machine configuration for the orange-pi-zero-2, based on Allwinner H616 CPU
+
+require conf/machine/include/sun50i-h616.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-h616-orangepi-zero2.dtb"
+UBOOT_MACHINE = "orangepi_zero2_defconfig"
+
+SPL_BINARY = "u-boot-sunxi-with-spl.bin"
+
+# as for now neither graphics nor audio is supported
+MACHINE_FEATURES:remove = "alsa x11"
+MACHINE_FEATURES:append = "bluetooth wifi"
+
+MACHINE_EXTRA_RRECOMMENDS = "uwe5622-firmware"

conf/machine/pcduino.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: pcduino-lite-wifi
+#@DESCRIPTION: Machine configuration for the pcDuino-Lite-Wifi, base on allwinner a10 CPU
+
+require conf/machine/include/sun4i.inc
+
+KERNEL_DEVICETREE = "sun4i-a10-pcduino.dtb"
+UBOOT_MACHINE = "Linksprite_pcDuino_defconfig"
+SUNXI_FEX_FILE = "sys_config/a10/pcduino.fex"

conf/machine/pcduino3.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: Linksprite A20-pcduino3 Board
+#@DESCRIPTION: Machine configuration for the pcDuino 3, based on Allwinner A20 CPU
+
+require conf/machine/include/sun7i.inc
+
+KERNEL_DEVICETREE = "sun7i-a20-pcduino3.dtb"
+UBOOT_MACHINE = "Linksprite_pcDuino3_defconfig"
+SUNXI_FEX_FILE = "sys_config/a20/linksprite_pcduino3.fex"

conf/machine/pine64-plus.conf

@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: pine64-plus
+#@DESCRIPTION: Machine configuration for the pine64-plus, based on Allwinner A64 CPU
+
+
+require conf/machine/include/sun50i.inc
+
+KERNEL_DEVICETREE = "allwinner/sun50i-a64-pine64-plus.dtb"
+UBOOT_MACHINE = "pine64_plus_defconfig"

recipes-bsp/sunxi-board-fex/sunxi-board-fex.bb

@@ -9,9 +9,9 @@ PR = "r0"
 
 COMPATIBLE_MACHINE = "(sun4i|sun5i|sun7i)"
 
-SRC_URI = "git://github.com/linux-sunxi/sunxi-boards.git;protocol=git"
+SRC_URI = "git://github.com/linux-sunxi/sunxi-boards.git;protocol=https;branch=master"
 # Increase PV with SRCREV change
-SRCREV = "496ef0fbd166cc2395daa76dd3c359357420963d"
+SRCREV = "af5f938ea14a3614d35ad3d9ab51a5d392117444"
 
 S = "${WORKDIR}/git"
 

recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend

@@ -0,0 +1,7 @@
+COMPATIBLE_MACHINE = "(sun50i|sun50i-h616|sun50i-h6)"
+
+TFA_PLATFORM:sun50i = "sun50i_a64"
+TFA_PLATFORM:sun50i-h6 = "sun50i_h6"
+TFA_PLATFORM:sun50i-h616 = "sun50i_h616"
+
+TFA_BUILD_TARGET = "bl31"

recipes-bsp/u-boot/files/0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch

@@ -0,0 +1,21 @@
+From 6a64d90ca4d976c16a2e102dbad0848e4d29776c Mon Sep 17 00:00:00 2001
+From: Florin Sarbu <florin@resin.io>
+Date: Wed, 12 Sep 2018 14:22:49 +0200
+Subject: [PATCH] nanopi_neo_air_defconfig: Enable eMMC support
+
+Upstream-Status: Pending
+Signed-off-by: Florin Sarbu <florin@resin.io>
+
+---
+ configs/nanopi_neo_air_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
+index 806d95c1cc..8899cc3a15 100644
+--- a/configs/nanopi_neo_air_defconfig
++++ b/configs/nanopi_neo_air_defconfig
+@@ -9,3 +9,4 @@ CONFIG_DRAM_CLK=408
+ CONFIG_CONSOLE_MUX=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_OHCI_HCD=y
++CONFIG_MMC_SUNXI_SLOT_EXTRA=2

recipes-bsp/u-boot/files/0002-Added-nanopi-r1-board-support.patch

@@ -0,0 +1,42 @@
+From 767a05572ef5b93c2e157749b1754cbe261ee43d Mon Sep 17 00:00:00 2001
+From: Marek Belisko <marek.belisko@open-nandra.com>
+Date: Fri, 8 Apr 2022 11:33:53 +0200
+Subject: [PATCH] Added nanopi-r1 board support
+
+Patch taken from : https://github.com/armbian/build/blob/master/patch/u-boot/u-boot-sunxi/add-nanopi-r1-and-duo2.patch
+
+Upstream-Status: Pending
+
+Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
+---
+diff --git a/configs/nanopi_r1_defconfig b/configs/nanopi_r1_defconfig
+new file mode 100644
+index 0000000..e028b41
+--- /dev/null
++++ b/configs/nanopi_r1_defconfig
+@@ -0,0 +1,22 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_H3=y
++CONFIG_DRAM_CLK=408
++CONFIG_DRAM_ZQ=3881979
++CONFIG_DRAM_ODT_EN=y
++CONFIG_MACPWR="PD6"
++# CONFIG_VIDEO_DE2 is not set
++CONFIG_NR_DRAM_BANKS=1
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_CONSOLE_MUX=y
++CONFIG_SYS_CLK_FREQ=480000000
++# CONFIG_CMD_FLASH is not set
++# CONFIG_SPL_DOS_PARTITION is not set
++# CONFIG_SPL_EFI_PARTITION is not set
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1"
++CONFIG_SUN8I_EMAC=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
++CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+-- 
+2.7.4
+

recipes-bsp/u-boot/files/0003-sunxi-H6-Enable-Ethernet-on-Orange-Pi-One-Plus.patch

@@ -0,0 +1,58 @@
+From: Anne Macedo <retpolanne@posteo.net>
+Date: Tue, 11 Jul 2023 00:39:58 +0000
+Subject: [PATCH] sunxi: H6: Enable Ethernet on Orange Pi One Plus
+
+Enable Ethernet on Orange Pi One Plus by using the correct phy for
+Realtek RTL8211E instead of the Generic One. Also use CONFIG_MACPWR to
+turn on ethernet on startup.
+
+After this patch is applied, a few issues can be seen:
+
+- there's still a PHY reset timed out error that doesn't seem to cause
+  any impacts to the overall connection
+
+- sometimes the emac driver times out after reset (yellow LED turns on
+  and never blinks)
+
+For future patches: for now, CONFIG_MACPWR is the only way to enable
+Ethernet on boot. There's already code on the dts for using the 3v3-gmac
+regulator. However, it is not probed on boot, so it only starts after a
+"regulator status" command is issued.
+
+More details about the troubleshooting on [1].
+
+Upstream-Status: Submitted
+
+[1] https://lore.kernel.org/u-boot/4wsvwgy56e2xfgtvioru2tf2ofkqprlts36qggivxogww6pn5j@4jk63zxhzhag/
+
+Signed-off-by: Anne Macedo <retpolanne@posteo.net>
+---
+ arch/arm/dts/sun50i-h6-orangepi-one-plus.dts | 2 +-
+ configs/orangepi_one_plus_defconfig          | 4 ++++
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
+index 29a081e72a..6427c58f8a 100644
+--- a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
++++ b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
+@@ -37,7 +37,7 @@
+ 
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+-		compatible = "ethernet-phy-ieee802.3-c22";
++		compatible = "ethernet-phy-id001c.c915", "ethernet-phy-ieee802.3-c22" ;
+ 		reg = <1>;
+ 	};
+ };
+diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig
+index aa5f540eb1..a1835492db 100644
+--- a/configs/orangepi_one_plus_defconfig
++++ b/configs/orangepi_one_plus_defconfig
+@@ -8,3 +8,7 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_OHCI_HCD=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_PHY_REALTEK=y
++CONFIG_PHY_ETHERNET_ID=y
++CONFIG_MACPWR="PD6"

recipes-bsp/u-boot/files/0004-OrangePi-3-LTS-support.patch

@@ -0,0 +1,420 @@
+From 9966dda20246285abf8b417bd251d5a4bea3e423 Mon Sep 17 00:00:00 2001
+From: Juliano Dorigão <jdorigao@gmail.com>
+Date: Fri, 3 Mar 2023 16:11:30 -0400
+Subject: [PATCH] OrangePi 3 LTS support
+
+---
+ arch/arm/dts/Makefile                     |   1 +
+ arch/arm/dts/sun50i-h6-orangepi-3-lts.dts | 361 ++++++++++++++++++++++
+ configs/orangepi_3_lts_defconfig          |  19 ++
+ 3 files changed, 381 insertions(+)
+ create mode 100644 arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
+ create mode 100644 configs/orangepi_3_lts_defconfig
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 43951a77..8dbbb6f4 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -710,6 +710,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
+ dtb-$(CONFIG_MACH_SUN50I_H6) += \
+ 	sun50i-h6-beelink-gs1.dtb \
+ 	sun50i-h6-orangepi-3.dtb \
++	sun50i-h6-orangepi-3-lts.dtb \
+ 	sun50i-h6-orangepi-lite2.dtb \
+ 	sun50i-h6-orangepi-one-plus.dtb \
+ 	sun50i-h6-pine-h64.dtb \
+diff --git a/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
+new file mode 100644
+index 00000000..67f38b8a
+--- /dev/null
++++ b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
+@@ -0,0 +1,361 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2023 Jernej Skrabec <jernej.skrabec@gmail.com>
++// Based on sun50i-h6-orangepi-3.dts, which is:
++// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-h6.dtsi"
++#include "sun50i-h6-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "OrangePi 3 LTS";
++	compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	ext_osc32k: ext_osc32k_clk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <32768>;
++		clock-output-names = "ext_osc32k";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "orangepi:red:power";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++
++		led-1 {
++			label = "orangepi:green:status";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the DC jack */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <150000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdca>;
++};
++
++&de {
++	status = "okay";
++};
++
++&dwc3 {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_gmac_3v3>;
++	allwinner,rx-delay-ps = <1500>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_bldo2>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_cldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_cldo1>;
++	vqmmc-supply = <&reg_bldo2>;
++	cap-mmc-hw-reset;
++	non-removable;
++	bus-width = <8>;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_bldo2>;
++	vcc-pd-supply = <&reg_cldo1>;
++	vcc-pg-supply = <&reg_bldo3>;
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&r_rsb {
++	clock-frequency = <100000>;
++	status = "okay";
++
++	axp805: pmic@745 {
++		compatible = "x-powers,axp805", "x-powers,axp806";
++		reg = <0x745>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		x-powers,self-working-mode;
++		vina-supply = <&reg_vcc5v>;
++		vinb-supply = <&reg_vcc5v>;
++		vinc-supply = <&reg_vcc5v>;
++		vind-supply = <&reg_vcc5v>;
++		vine-supply = <&reg_vcc5v>;
++		aldoin-supply = <&reg_vcc5v>;
++		bldoin-supply = <&reg_vcc5v>;
++		cldoin-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-pl-led-ir";
++			};
++
++			reg_aldo2: aldo2 {
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-audio-tv-ephy-mac";
++			};
++
++			/* ALDO3 is shorted to CLDO1 */
++			reg_aldo3: aldo3 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
++			};
++
++			reg_bldo1: bldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18-dram-bias-pll";
++			};
++
++			reg_bldo2: bldo2 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-efuse-pcie-hdmi-pc";
++			};
++
++			reg_bldo3: bldo3 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-pm-pg-dcxoio-wifi";
++			};
++
++			bldo4 {
++				/* unused */
++			};
++
++			reg_cldo1: cldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
++			};
++
++			cldo2 {
++				/* unused */
++			};
++
++			cldo3 {
++				/* unused */
++			};
++
++			reg_dcdca: dcdca {
++				regulator-always-on;
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1160000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdcc: dcdcc {
++				regulator-enable-ramp-delay = <32000>;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1080000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-gpu";
++			};
++
++			reg_dcdcd: dcdcd {
++				regulator-always-on;
++				regulator-min-microvolt = <980000>;
++				regulator-max-microvolt = <980000>;
++				regulator-name = "vdd-sys";
++			};
++
++			reg_dcdce: dcdce {
++				regulator-always-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-name = "vcc-dram";
++			};
++
++			sw {
++				/* unused */
++			};
++		};
++	};
++};
++
++&pwm {
++	status = "okay";
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&rtc {
++	clocks = <&ext_osc32k>;
++};
++
++/delete-node/ &spi0;
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&usb2otg {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usb2phy {
++	usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++	usb0_vbus-supply = <&reg_vcc5v>;
++	usb3_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&usb3phy {
++	status = "okay";
++};
+diff --git a/configs/orangepi_3_lts_defconfig b/configs/orangepi_3_lts_defconfig
+new file mode 100644
+index 00000000..41a9af4e
+--- /dev/null
++++ b/configs/orangepi_3_lts_defconfig
+@@ -0,0 +1,19 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3-lts"
++CONFIG_SPL=y
++CONFIG_MACH_SUN50I_H6=y
++CONFIG_SUNXI_DRAM_H6_LPDDR3=y
++CONFIG_MMC0_CD_PIN="PF6"
++CONFIG_MMC_SUNXI_SLOT_EXTRA=2
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_SPL_STACK=0x118000
++CONFIG_SYS_PBSIZE=1024
++CONFIG_SYS_BOOTM_LEN=0x2000000
++CONFIG_PHY_SUN50I_USB3=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
+-- 
+2.39.2
+

recipes-bsp/u-boot/files/aarch64/boot.cmd

@@ -0,0 +1,11 @@
+# Default to (primary) SD
+rootdev=mmcblk0p2
+if itest.b *0x28 == 0x02 ; then
+	# U-Boot loaded from eMMC or secondary SD so use it for rootfs too
+	echo "U-boot loaded from eMMC or secondary SD"
+	rootdev=mmcblk1p2
+fi
+setenv bootargs console=${console} console=tty1 root=/dev/${rootdev} rootwait panic=10 ${extra}
+load mmc 0:1 ${fdt_addr_r} ${fdtfile}
+load mmc 0:1 ${kernel_addr_r} Image
+booti ${kernel_addr_r} - ${fdt_addr_r}

recipes-bsp/u-boot/files/arm/boot.cmd

@@ -0,0 +1,11 @@
+# Default to (primary) SD
+rootdev=mmcblk0p2
+if itest.b *0x28 == 0x02 ; then
+	# U-Boot loaded from eMMC or secondary SD so use it for rootfs too
+	echo "U-boot loaded from eMMC or secondary SD"
+	rootdev=mmcblk1p2
+fi
+setenv bootargs console=${console} console=tty1 root=/dev/${rootdev} rootwait panic=10 ${extra}
+load mmc 0:1 ${fdt_addr_r} ${fdtfile} || load mmc 0:1 ${fdt_addr_r} boot/allwinner/${fdtfile}
+load mmc 0:1 ${kernel_addr_r} zImage || load mmc 0:1 ${kernel_addr_r} boot/zImage || load mmc 0:1 ${kernel_addr_r} uImage || load mmc 0:1 ${kernel_addr_r} boot/uImage
+bootz ${kernel_addr_r} - ${fdt_addr_r} || bootm ${kernel_addr_r} - ${fdt_addr_r}

recipes-bsp/u-boot/files/bananapi-m64/boot.cmd

@@ -0,0 +1,11 @@
+# Default to (primary) SD
+rootdev=mmcblk0p2
+if itest.b *0x28 == 0x02 ; then
+	# U-Boot loaded from eMMC or secondary SD so use it for rootfs too
+	echo "U-boot loaded from eMMC or secondary SD"
+	rootdev=mmcblk2p2
+fi
+setenv bootargs console=${console} console=tty1 root=/dev/${rootdev} rootwait panic=10 ${extra}
+load mmc 0:1 ${fdt_addr_r} ${fdtfile}
+load mmc 0:1 ${kernel_addr_r} Image
+booti ${kernel_addr_r} - ${fdt_addr_r}

recipes-bsp/u-boot/files/boot.cmd

@@ -1,4 +0,0 @@
-setenv bootargs console=${console} console=tty1 root=/dev/mmcblk0p2 rootwait panic=10 ${extra}
-load mmc 0:1 ${fdt_addr_r} ${fdtfile} || load mmc 0:1 ${fdt_addr_r} boot/${fdtfile}
-load mmc 0:1 ${kernel_addr_r} zImage || load mmc 0:1 ${kernel_addr_r} boot/zImage || load mmc 0:1 ${kernel_addr_r} uImage || load mmc 0:1 ${kernel_addr_r} boot/uImage
-bootz ${kernel_addr_r} - ${fdt_addr_r} || bootm ${kernel_addr_r} - ${fdt_addr_r}

recipes-bsp/u-boot/u-boot-sunxi.bb

@@ -2,7 +2,7 @@ DESCRIPTION = "U-Boot port for sunxi"
 
 require recipes-bsp/u-boot/u-boot.inc
 
-LICENSE = "GPLv2"
+LICENSE = "GPL-2.0-only"
 LIC_FILES_CHKSUM = "file://Licenses/gpl-2.0.txt;md5=b234ee4d69f5fce4486a80fdaf4a4263"
 
 # No patches for other machines yet
@@ -19,8 +19,10 @@ UBOOT_MACHINE_olinuxino-a10s = "A10s-OLinuXino-Micro_config"
 UBOOT_MACHINE_meleg = "Mele_A1000G_config"
 
 SRC_URI = " \
-	git://github.com/linux-sunxi/u-boot-sunxi.git;protocol=git;branch=sunxi \
-	file://0002-gcc5-fixes.patch \
+	git://github.com/linux-sunxi/u-boot-sunxi.git;protocol=https;branch=sunxi \
+	file://0001-gcc5-fixes.patch \
+	file://0002-gcc6-fixes.patch \
+	file://0003-No-gcc-version-specific-includes.patch \
 	"
 
 PE = "1"
@@ -34,3 +36,7 @@ S = "${WORKDIR}/git"
 PACKAGE_ARCH = "${MACHINE_ARCH}"
 
 SPL_BINARY="u-boot-sunxi-with-spl.bin"
+
+do_configure () {
+    oe_runmake -C ${S} O=${B} ${UBOOT_MACHINE}
+}

recipes-bsp/u-boot/u-boot-sunxi/0002-gcc6-fixes.patch

@@ -1,8 +1,7 @@
-Index: git/include/linux/compiler-gcc5.h
-===================================================================
---- git/include/linux/compiler-gcc5.h    2015-09-19 20:11:27.999423338 +0200
-+++ git/include/linux/compiler-gcc5.h    2015-09-23 10:26:05.000000000 +0200
-@@ -0,0 +1,66 @@
+diff -urN git-ORIG/include/linux/compiler-gcc6.h git/include/linux/compiler-gcc6.h
+--- git-ORIG/include/linux/compiler-gcc6.h	1969-12-31 19:00:00.000000000 -0500
++++ git/include/linux/compiler-gcc6.h	2017-04-09 19:50:16.920945874 -0400
+@@ -0,0 +1,65 @@
 +#ifndef __LINUX_COMPILER_H
 +#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
 +#endif
@@ -58,7 +57,6 @@ Index: git/include/linux/compiler-gcc5.h
 + *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
 + *
 + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ * Fixed in GCC 4.8.2 and later versions.
 + *
 + * (asm goto is automatically volatile - the naming reflects this.)
 + */

recipes-bsp/u-boot/u-boot-sunxi/0003-No-gcc-version-specific-includes.patch

@@ -0,0 +1,24 @@
+From bc4aa5814cbedbfaa1c79dfe7ea2571fee7f2d51 Mon Sep 17 00:00:00 2001
+From: Andrey Lebedev <andrey@lebedev.lt>
+Date: Wed, 22 Jan 2020 20:00:11 +0200
+Subject: [PATCH] No gcc version-specific includes
+
+In order to support gcc-5 and above. Fixes compilation errors like
+
+linux/compiler-gcc9.h: No such file or directory
+---
+ include/linux/compiler-gcc.h | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
+index 9896e547b9..5f0bd65f3a 100644
+--- a/include/linux/compiler-gcc.h
++++ b/include/linux/compiler-gcc.h
+@@ -90,4 +90,3 @@
+ #define __gcc_header(x) #x
+ #define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
+ #define gcc_header(x) _gcc_header(x)
+-#include gcc_header(__GNUC__)
+-- 
+2.20.1
+

recipes-bsp/u-boot/u-boot_%.bbappend

@@ -0,0 +1,32 @@
+FILESEXTRAPATHS:prepend:sunxi := "${THISDIR}/files:"
+
+DEPENDS:append:sunxi = " bc-native dtc-native swig-native python3-native flex-native bison-native "
+DEPENDS:append:sun50i = " trusted-firmware-a"
+
+COMPATIBLE_MACHINE:sunxi = "(sun4i|sun5i|sun7i|sun8i|sun50i)"
+
+DEFAULT_PREFERENCE:sun4i = "1"
+DEFAULT_PREFERENCE:sun5i = "1"
+DEFAULT_PREFERENCE:sun7i = "1"
+DEFAULT_PREFERENCE:sun8i = "1"
+DEFAULT_PREFERENCE:sun50i = "1"
+
+SRC_URI:append:sunxi = " \
+        file://0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch \
+	file://0002-Added-nanopi-r1-board-support.patch \
+	file://0003-sunxi-H6-Enable-Ethernet-on-Orange-Pi-One-Plus.patch \
+        file://0004-OrangePi-3-LTS-support.patch \
+        file://boot.cmd \
+"
+
+UBOOT_ENV_SUFFIX:sunxi = "scr"
+UBOOT_ENV:sunxi = "boot"
+
+EXTRA_OEMAKE:append:sunxi = ' HOSTLDSHARED="${BUILD_CC} -shared ${BUILD_LDFLAGS} ${BUILD_CFLAGS}" '
+EXTRA_OEMAKE:append:sun50i = " BL31=${DEPLOY_DIR_IMAGE}/bl31.bin SCP=/dev/null"
+
+do_compile:sun50i[depends] += "trusted-firmware-a:do_deploy"
+
+do_compile:append:sunxi() {
+    ${B}/tools/mkimage -C none -A arm -T script -d ${WORKDIR}/boot.cmd ${WORKDIR}/${UBOOT_ENV_BINARY}
+}

recipes-bsp/u-boot/u-boot_2015.10.bb

@@ -1,44 +0,0 @@
-DESCRIPTION="Upstream's U-boot configured for sunxi devices"
-
-require recipes-bsp/u-boot/u-boot.inc
-
-DEPENDS += "dtc-native"
-
-LICENSE = "GPLv2"
-
-LIC_FILES_CHKSUM = "\
-file://Licenses/Exceptions;md5=338a7cb1e52d0d1951f83e15319a3fe7 \
-file://Licenses/bsd-2-clause.txt;md5=6a31f076f5773aabd8ff86191ad6fdd5 \
-file://Licenses/bsd-3-clause.txt;md5=4a1190eac56a9db675d58ebe86eaf50c \
-file://Licenses/eCos-2.0.txt;md5=b338cb12196b5175acd3aa63b0a0805c \
-file://Licenses/gpl-2.0.txt;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
-file://Licenses/ibm-pibs.txt;md5=c49502a55e35e0a8a1dc271d944d6dba \
-file://Licenses/isc.txt;md5=ec65f921308235311f34b79d844587eb \
-file://Licenses/lgpl-2.0.txt;md5=5f30f0716dfdd0d91eb439ebec522ec2 \
-file://Licenses/lgpl-2.1.txt;md5=4fbd65380cdd255951079008b364516c \
-file://Licenses/x11.txt;md5=b46f176c847b8742db02126fb8af92e2 \
-"
-
-COMPATIBLE_MACHINE = "(sun4i|sun5i|sun7i)"
-
-DEFAULT_PREFERENCE_sun4i="1"
-DEFAULT_PREFERENCE_sun5i="1"
-DEFAULT_PREFERENCE_sun7i="1"
-
-SRC_URI += "file://boot.cmd \
-"
-
-SRCREV = "5ec0003b19cbdf06ccd6941237cbc0d1c3468e2d"
-
-PV = "v2015.10${SRCPV}"
-
-PE = "1"
-
-SPL_BINARY="u-boot-sunxi-with-spl.bin"
-
-UBOOT_ENV_SUFFIX = "scr"
-UBOOT_ENV = "boot"
-
-do_compile_append() {
-    ${S}/tools/mkimage -C none -A arm -T script -d ${WORKDIR}/boot.cmd ${WORKDIR}/${UBOOT_ENV_BINARY}
-}

recipes-devtools/python/files/olinuxino-a20som/mapping.h

@@ -0,0 +1,265 @@
+/*
+ *
+ * This file is part of pyA20SOM.
+ * mapping.h is python GPIO extension.
+ *
+ * Copyright (c) 2014 Stefan Mavrodiev @ OLIMEX LTD, <support@olimex.com>
+ *
+ * pyA20SOM is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MAPPING_H
+#define __MAPPING_H
+
+#include "gpio_lib.h"
+
+/**
+Structure that describe all gpio
+*/
+typedef struct _pin {
+    char name[10];          // The processor pin
+    int offset;             // Memory offset for the pin
+    int pin_number;         // Number on the connector
+}pin_t;
+
+typedef struct _gpio {
+    char connector_name[10];
+    pin_t pins[41];
+}gpio_t;
+
+
+gpio_t gpio[] = {
+    {"lcd",
+        {
+            {   "PD16", SUNXI_GPD(16),  5   },
+            {   "PD17", SUNXI_GPD(17),  6   },
+            {   "PD18", SUNXI_GPD(18),  7   },
+            {   "PD19", SUNXI_GPD(19),  8   },
+            {   "PD20", SUNXI_GPD(20),  9   },
+            {   "PD21", SUNXI_GPD(21),  10  },
+            {   "PD22", SUNXI_GPD(22),  11  },
+            {   "PD23", SUNXI_GPD(23),  12  },
+            {   "PD8", SUNXI_GPD(8),    13  },
+            {   "PD9", SUNXI_GPD(9),    14  },
+            {   "PD10", SUNXI_GPD(10),  15  },
+            {   "PD11", SUNXI_GPD(11),  16  },
+            {   "PD12", SUNXI_GPD(12),  17  },
+            {   "PD13", SUNXI_GPD(13),  18  },
+            {   "PD14", SUNXI_GPD(14),  19  },
+            {   "PD15", SUNXI_GPD(15),  20  },
+            {   "PD0",  SUNXI_GPD(0),   21  },
+            {   "PD1",  SUNXI_GPD(1),   22  },
+            {   "PD2",  SUNXI_GPD(2),   23  },
+            {   "PD3",  SUNXI_GPD(3),   24  },
+            {   "PD4",  SUNXI_GPD(4),   25  },
+            {   "PD5",  SUNXI_GPD(5),   26  },
+            {   "PD6",  SUNXI_GPD(6),   27  },
+            {   "PD7",  SUNXI_GPD(7),   28  },
+            {   "PD26", SUNXI_GPD(26),  29  },
+            {   "PD27", SUNXI_GPD(27),  30  },
+            {   "PD24", SUNXI_GPD(24),  31  },
+            {   "PD25", SUNXI_GPD(25),  32  },
+            {   "PH7",  SUNXI_GPH(7),   35  },
+            {   "PB2",  SUNXI_GPB(2),   36  },
+            {
+                {   0,  0,  0}
+            },
+        }
+    },
+    {"gpio1",
+        {
+            {   "PB9",  SUNXI_GPB(9),   7   },
+            {   "PH5",  SUNXI_GPH(5),   9   },
+            {   "PH4",  SUNXI_GPH(4),   11  },
+            {   "PH6",  SUNXI_GPH(6),   13  },
+            {   "PH3",  SUNXI_GPH(3),   15  },
+            {   "PI0",  SUNXI_GPI(0),   29  },
+            {   "PI1",  SUNXI_GPI(1),   31  },
+            {   "PI2",  SUNXI_GPI(2),   33  },
+            {   "PI3",  SUNXI_GPI(3),   35  },
+            {   "PI10", SUNXI_GPI(10),  37  },
+            {   "PI11", SUNXI_GPI(11),  39  },
+            {   "PI14", SUNXI_GPI(14),  40  },
+            {
+                {   0,  0,  0}
+            },
+        }
+    },
+    {"gpio2",
+        {
+            {   "PB22", SUNXI_GPB(22),  21  },
+            {   "PB23", SUNXI_GPB(23),  22  },
+            {   "PA0",  SUNXI_GPA(0),   29  },
+            {   "PA1",  SUNXI_GPA(1),   27  },
+            {   "PA2",  SUNXI_GPA(2),   25  },
+            {   "PA3",  SUNXI_GPA(3),   23  },
+            {   "PA4",  SUNXI_GPA(4),   30  },
+            {   "PA5",  SUNXI_GPA(5),   28  },
+            {   "PA6",  SUNXI_GPA(6),   26  },
+            {   "PA7",  SUNXI_GPA(7),   24  },
+            {   "PA8",  SUNXI_GPA(8),   33  },
+            {   "PA9",  SUNXI_GPA(9),   35  },
+            {   "PA10", SUNXI_GPA(10),  31  },
+            {   "PA11", SUNXI_GPA(11),  37  },
+            {   "PA12", SUNXI_GPA(12),  39  },
+            {   "PA13", SUNXI_GPA(13),  32  },
+            {   "PA14", SUNXI_GPA(14),  34  },
+            {   "PA15", SUNXI_GPA(15),  36  },
+            {   "PA16", SUNXI_GPA(16),  38  },
+            {   "PA17", SUNXI_GPA(17),  40  },
+
+            {
+                {   0,  0,  0}
+            },
+        }
+    },
+
+    {"gpio3",
+        {
+            {   "PH0",  SUNXI_GPH(0),   5   },
+            {   "PH2",  SUNXI_GPH(2),   7   },
+            {   "PH8",  SUNXI_GPH(8),   9   },
+            {   "PH9",  SUNXI_GPH(9),   11  },
+            {   "PH10", SUNXI_GPH(10),  13  },
+            {   "PH11", SUNXI_GPH(11),  15  },
+            {   "PH12", SUNXI_GPH(12),  17  },
+            {   "PH13", SUNXI_GPH(13),  19  },
+            {   "PH14", SUNXI_GPH(14),  21  },
+            {   "PH15", SUNXI_GPH(15),  23  },
+            {   "PH16", SUNXI_GPH(16),  25  },
+            {   "PH17", SUNXI_GPH(17),  27  },
+            {   "PH18", SUNXI_GPH(18),  29  },
+            {   "PH19", SUNXI_GPH(19),  31  },
+            {   "PH20", SUNXI_GPH(20),  33  },
+            {   "PH21", SUNXI_GPH(21),  35  },
+            {   "PH22", SUNXI_GPH(22),  37  },
+            {   "PH23", SUNXI_GPH(23),  39  },
+
+            {   "PB3",  SUNXI_GPB(3),   6   },
+            {   "PB4",  SUNXI_GPB(4),   8   },
+            {   "PB5",  SUNXI_GPB(5),   10  },
+            {   "PB6",  SUNXI_GPB(6),   12  },
+            {   "PB7",  SUNXI_GPB(7),   14  },
+            {   "PB8",  SUNXI_GPB(8),   16  },
+            {   "PB10",  SUNXI_GPB(10), 18  },
+            {   "PB11",  SUNXI_GPB(11), 20  },
+            {   "PB12",  SUNXI_GPB(12), 22  },
+            {   "PB13",  SUNXI_GPB(13), 24  },
+            {   "PB14",  SUNXI_GPB(14), 26  },
+            {   "PB15",  SUNXI_GPB(15), 28  },
+            {   "PB16",  SUNXI_GPB(16), 30  },
+            {   "PB17",  SUNXI_GPB(17), 32  },
+            {   "PH24",  SUNXI_GPH(24), 34  },
+            {   "PH25",  SUNXI_GPH(25), 36  },
+            {   "PH26",  SUNXI_GPH(26), 38  },
+            {   "PH27",  SUNXI_GPH(27), 40  },
+            {
+                {   0,  0,  0}
+            },
+        }
+    },
+
+    {"gpio4",
+        {
+            {   "PB0",  SUNXI_GPB(0),   5   },
+            {   "PB1",  SUNXI_GPB(1),   7   },
+            {   "PE0",  SUNXI_GPE(0),   6   },
+            {   "PE1",  SUNXI_GPE(1),   8   },
+            {   "PE2",  SUNXI_GPE(2),   10  },
+            {   "PE3",  SUNXI_GPE(3),   12  },
+            {   "PE4",  SUNXI_GPE(4),   14  },
+            {   "PE5",  SUNXI_GPE(5),   16  },
+            {   "PE6",  SUNXI_GPE(0),   18  },
+            {   "PE7",  SUNXI_GPE(0),   9   },
+            {   "PE8",  SUNXI_GPE(0),   11  },
+            {   "PE9",  SUNXI_GPE(0),   13  },
+            {   "PE10", SUNXI_GPE(0),   15  },
+            {   "PE11", SUNXI_GPE(0),   17  },
+            {   "PI20", SUNXI_GPI(20),  19  },
+            {   "PI21", SUNXI_GPI(21),  20  },
+            {   "PB18",  SUNXI_GPB(18), 21  },
+            {   "PB19",  SUNXI_GPB(19), 22  },
+            {   "PI16",  SUNXI_GPI(16), 23  },
+            {   "PI17",  SUNXI_GPI(17), 24  },
+            {   "PI18",  SUNXI_GPI(18), 25  },
+            {   "PI19",  SUNXI_GPI(19), 26  },
+            {   "PI12",  SUNXI_GPI(12), 27  },
+            {   "PI13",  SUNXI_GPI(13), 28  },
+            {   "PB20",  SUNXI_GPB(20), 29  },
+            {   "PB21",  SUNXI_GPB(21), 30  },
+            {   "PC22",  SUNXI_GPC(22), 31  },
+            {   "PC21",  SUNXI_GPC(21), 32  },
+            {   "PC20",  SUNXI_GPC(20), 33  },
+            {   "PC19",  SUNXI_GPC(21), 34  },
+            {   "PI15",  SUNXI_GPI(15), 36  },
+            {
+                {   0,  0,  0}
+            },
+        }
+    },
+
+    {"gpio5",
+        {
+            {   "PG0",  SUNXI_GPG(0),   1   },
+            {   "PG1",  SUNXI_GPG(1),   3   },
+            {   "PG2",  SUNXI_GPG(2),   5   },
+            {   "PG3",  SUNXI_GPG(3),   7   },
+            {   "PG4",  SUNXI_GPG(4),   9   },
+            {   "PG5",  SUNXI_GPG(5),   11  },
+            {   "PG6",  SUNXI_GPG(6),   13  },
+            {   "PG7",  SUNXI_GPG(7),   15  },
+            {   "PG8",  SUNXI_GPG(8),   17  },
+            {   "PG9",  SUNXI_GPG(9),   19  },
+            {   "PG10", SUNXI_GPG(10),  21  },
+            {   "PG11", SUNXI_GPG(11),  23  },
+            {   "PC8",  SUNXI_GPC(8),   25  },
+            {   "PC9",  SUNXI_GPC(9),   27  },
+            {   "PC10", SUNXI_GPC(10),  29  },
+            {   "PC11", SUNXI_GPC(11),  31  },
+            {   "PC12", SUNXI_GPC(12),  33  },
+            {   "PC13", SUNXI_GPC(13),  35  },
+            {   "PC14", SUNXI_GPC(14),  37  },
+            {   "PC15", SUNXI_GPC(15),  39  },
+            {   "PI6",  SUNXI_GPI(6),   4   },
+            {   "PI7",  SUNXI_GPI(7),   6   },
+            {   "PI8",  SUNXI_GPI(8),   8   },
+            {   "PI9",  SUNXI_GPI(9),   10  },
+            {   "PI4",  SUNXI_GPI(4),   12  },
+            {   "PI5",  SUNXI_GPI(5),   14  },
+            {   "PC16", SUNXI_GPC(16),  16  },
+            {   "PC17", SUNXI_GPC(17),  18  },
+            {   "PC18", SUNXI_GPC(18),  20  },
+            {   "PC23", SUNXI_GPC(23),  22  },
+            {   "PC24", SUNXI_GPC(24),  24  },
+            {   "PC7",  SUNXI_GPC(7),   26  },
+            {   "PC6",  SUNXI_GPC(6),   28  },
+            {   "PC5",  SUNXI_GPC(5),   30  },
+            {   "PC3",  SUNXI_GPC(3),   32  },
+            {   "PC2",  SUNXI_GPC(2),   34  },
+            {   "PC1",  SUNXI_GPC(1),   36  },
+            {   "PC0",  SUNXI_GPC(0),   38  },
+            {   "PC4",  SUNXI_GPC(4),   40  },
+            {
+                {   0,  0,  0}
+            },
+        }
+    },
+
+};
+
+
+
+#endif

recipes-devtools/python/files/setup.py.patch

@@ -1,51 +0,0 @@
---- pyA20-0.2.0/setup.py	2014-09-04 12:17:18.000000000 +0200
-+++ pyA20-0.2.0/setup.py	2014-11-24 17:44:37.000000000 +0100
-@@ -43,31 +43,31 @@
-     Detect processor type
-     :return:
-     """
--    cpuinfo = open("/proc/cpuinfo", 'r')
--    for line in cpuinfo:
--        if "Hardware" in line:
--            processor = line.split(":")[1].rstrip()
-+    #cpuinfo = open("/proc/cpuinfo", 'r')
-+    #for line in cpuinfo:
-+    #    if "Hardware" in line:
-+    #        processor = line.split(":")[1].rstrip()
- 
--            if "sun4i" in processor:
--                print ("Detected processor: " + print_color(processor) + " (Probably Allwinner A10)")
-+    #        if "sun4i" in processor:
-+    #            print ("Detected processor: " + print_color(processor) + " (Probably Allwinner A10)")
- 
--            elif "sun5i" in processor:
--                print ("Detected processor: " + print_color(processor) + " (Probably Allwinner A13)")
-+    #        elif "sun5i" in processor:
-+    #            print ("Detected processor: " + print_color(processor) + " (Probably Allwinner A13)")
- 
--            elif "sun7i" in processor:
--                print ("Detected processor: " + print_color(processor) + " (Probably Allwinner A20)")
-+    #        elif "sun7i" in processor:
-+    #            print ("Detected processor: " + print_color(processor) + " (Probably Allwinner A20)")
- 
--            else:
--                print ("Detected processor: " + print_color("unknown"))
-+    #        else:
-+    #            print ("Detected processor: " + print_color("unknown"))
- 
- 
--            if processor_type not in processor:
--                print_warning()
-+    #        if processor_type not in processor:
-+    #            print_warning()
- 
--            return
-+    return
- 
--    print ("No processor detected")
--    print_warning()
-+    #print ("No processor detected")
-+    #print_warning()
- 
- 
- class build_ext(_build_ext):

recipes-devtools/python/pya20_0.2.12.bb

@@ -1,24 +1,23 @@
 DESCRIPTION = "A module to control Allwinner GPIO,SPI and I2C channels"
 HOMEPAGE = "https://pypi.python.org/pypi/pyA20"
 SECTION = "devel/python"
-LICENSE = "MIT"
-LIC_FILES_CHKSUM = "file://PKG-INFO;md5=b4cb7d5da6f1efc1d0bf487169e83985"
-DEPENDS = "python"
+LICENSE = "GPL-3.0-only"
+LIC_FILES_CHKSUM = "file://PKG-INFO;md5=4e584373bb0f46ef1e423cb7df37847d"
+DEPENDS = "python3"
 
 # No GPIO mappings for other machines yet
-COMPATIBLE_MACHINE = "(olinuxino-a13|olinuxino-a10|olinuxino-a20|olinuxino-a10lime|olinuxino-a20lime|olinuxino-a20lime2|olinuxino-a13som)"
+COMPATIBLE_MACHINE = "(olinuxino-a13|olinuxino-a10|olinuxino-a20|olinuxino-a10lime|olinuxino-a20lime|olinuxino-a20lime2|olinuxino-a13som|olinuxino-a20som)"
 
-SRC_URI = "http://pypi.python.org/packages/source/p/pyA20/pyA20-${PV}.tar.gz \
-           file://setup.py.patch \
+SRC_URI = "https://pypi.python.org/packages/source/p/pyA20/pyA20-${PV}.tar.gz \
            file://mapping.h \
           "
 S = "${WORKDIR}/pyA20-${PV}"
 
-inherit distutils
+inherit distutils3
 
-do_compile_prepend() { 
+do_compile:prepend() { 
 cp ${WORKDIR}/mapping.h ${S}/pyA20/gpio/mapping.h
 }
 
-SRC_URI[md5sum] = "b4115859834f09ebd389f810f2ffefb9"
-SRC_URI[sha256sum] = "9855747d9bbdfcce6b460fcd67d953155e39f4e002a9a4c573910248b451dad8"
+SRC_URI[md5sum] = "cab03b4931199804603d1074f6d8f48f"
+SRC_URI[sha256sum] = "4bef559a9c5a4d648d9834bad996cf2805b20d6063b8051029ffdf9deda2b536"

recipes-graphics/libgles/sunxi-mali_git.bb

@@ -3,16 +3,26 @@ DESCRIPTION = "libGLES for the A10/A13 Allwinner processor with Mali 400 (X11)"
 LICENSE = "Proprietary"
 LIC_FILES_CHKSUM = "file://README;md5=1b81a178e80ee888ee4571772699ab2c"
 
-COMPATIBLE_MACHINE = "(sun4i|sun5i|sun7i)"
+COMPATIBLE_MACHINE = "(sun4i|sun5i|sun7i|sun8i)"
 
 # These libraries shouldn't get installed in world builds unless something
 # explicitly depends upon them.
 EXCLUDE_FROM_WORLD = "1"
 PROVIDES = "virtual/libgles1 virtual/libgles2 virtual/egl"
-RPROVIDES_${PN} += "libGLESv2.so libEGL.so libGLESv2.so libGLESv1_CM.so libMali.so"
 
-SRCREV_pn-${PN} = "d343311efc8db166d8371b28494f0f27b6a58724"
-SRC_URI = "gitsm://github.com/linux-sunxi/sunxi-mali.git \
+# There's only hardfp version available
+python __anonymous() {
+    tunes = d.getVar("TUNE_FEATURES", True)
+    if not tunes:
+        return
+    if "callconvention-hard" not in tunes:
+        pkgn = d.getVar("PN", True)
+        pkgv = d.getVar("PV", True)
+        raise bb.parse.SkipPackage("%s-%s ONLY supports hardfp mode for now" % (pkgn, pkgv))
+}
+
+SRCREV = "d343311efc8db166d8371b28494f0f27b6a58724"
+SRC_URI = "git://github.com/linux-sunxi/sunxi-mali.git;protocol=https;branch=master \
            file://0001-Add-EGLSyncKHR-EGLTimeKHR-and-GLChar-definition.patch \
            file://0002-Add-missing-GLchar-definition.patch \
            file://0003-Fix-sed-to-replace-by-the-correct-var.patch \
@@ -21,9 +31,9 @@ SRC_URI = "gitsm://github.com/linux-sunxi/sunxi-mali.git \
 
 S = "${WORKDIR}/git"
 
-DEPENDS = "libdrm dri2proto libump"
+DEPENDS = "libdrm xorgproto libump patchelf-native"
 
-PACKAGECONFIG ??= "${@base_contains('DISTRO_FEATURES', 'x11', 'x11', '', d)} ${@base_contains('DISTRO_FEATURES', 'wayland', 'wayland', '', d)}"
+PACKAGECONFIG ??= "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11', '', d)} ${@bb.utils.contains('DISTRO_FEATURES', 'wayland', 'wayland', '', d)}"
 PACKAGECONFIG[wayland] = "EGL_TYPE=framebuffer,,,"
 PACKAGECONFIG[x11] = "EGL_TYPE=x11,,virtual/libx11 libxau libxdmcp libdri2,"
 
@@ -33,7 +43,7 @@ INHIBIT_PACKAGE_STRIP = "1"
 INHIBIT_SYSROOT_STRIP = "1"
 
 do_configure() {
-         DESTDIR=${D}/ VERSION=r3p0 ABI=armhf ${EXTRA_OECONF} make config
+         DESTDIR=${D}/ VERSION=r3p0 ABI=armhf make ${EXTRA_OEMAKE} config
 }
 
 do_install() {
@@ -60,11 +70,13 @@ do_install() {
 
     make libdir=${D}${libdir}/ includedir=${D}${includedir}/ install
     make libdir=${D}${libdir}/ includedir=${D}${includedir}/ install -C include
+    rm -f ${D}${includedir}/KHR/khrplatform.h
 
     # Fix .so name and create symlinks, binary package provides .so wich can't be included directly in package without triggering the 'dev-so' QA check
     # Packages like xf86-video-fbturbo dlopen() libUMP.so, so we do need to ship the .so files in ${PN}
 
     mv ${D}${libdir}/libMali.so ${D}${libdir}/libMali.so.3
+    patchelf --set-soname libMali.so.3 ${D}${libdir}/libMali.so.3
     ln -sf libMali.so.3 ${D}${libdir}/libMali.so
 
     for flib in libEGL.so.1.4 libGLESv1_CM.so.1.1 libGLESv2.so.2.0 ; do
@@ -72,15 +84,21 @@ do_install() {
         ln -sf libMali.so.3 ${D}${libdir}/$flib
     done
 
-    DESTDIR=${D}/ VERSION=r3p0 ABI=armhf ${EXTRA_OECONF} make test
+    DESTDIR=${D}/ VERSION=r3p0 ABI=armhf make ${EXTRA_OEMAKE} test
     install -d ${D}${bindir}
     install -m 0755 ${S}/test/test ${D}${bindir}/sunximali-test
 }
 
 # Packages like xf86-video-fbturbo dlopen() libUMP.so, so we do need to ship the .so files in ${PN}
 PACKAGES =+ "${PN}-test"
-FILES_${PN} += "${libdir}/lib*.so"
-FILES_${PN}-dev = "${includedir} ${libdir}/pkgconfig/*"
-FILES_${PN}-test = "${bindir}/sunximali-test"
+
+RPROVIDES:${PN} += "libGLESv2.so libEGL.so libGLESv2.so libGLESv1_CM.so libMali.so"
+RDEPENDS:${PN}-test = "${PN}"
+
+FILES:${PN} += "${libdir}/lib*.so"
+FILES:${PN}-dev = "${includedir} ${libdir}/pkgconfig/*"
+FILES:${PN}-test = "${bindir}/sunximali-test"
+
 # These are closed binaries generated elsewhere so don't check ldflags & text relocations
-INSANE_SKIP_${PN} = "dev-so ldflags textrel"
+INSANE_SKIP:${PN} = "dev-so ldflags textrel"
+INSANE_SKIP:${PN}-test = "dev-so ldflags textrel"

recipes-graphics/libump/libump_git.bb

@@ -1,14 +1,14 @@
 DESCRIPTION = "Unified Memory Provider userspace API source code needed for xf86-video-mali compilation"
 
-LICENSE = "Apache-2"
+LICENSE = "Apache-2.0"
 LIC_FILES_CHKSUM = "file://debian/copyright;md5=edf7fb6071cae7ec80d537a05ee17198"
 
 inherit autotools
 
 PV = "r4p0-00rel0+git${SRCPV}"
-SRCREV_pn-${PN} = "ec0680628744f30b8fac35e41a7bd8e23e59c39f"
+SRCREV = "ec0680628744f30b8fac35e41a7bd8e23e59c39f"
 
-SRC_URI = "git://github.com/linux-sunxi/libump.git"
+SRC_URI = "git://github.com/linux-sunxi/libump.git;protocol=https;branch=master"
 
 S = "${WORKDIR}/git"
 

recipes-graphics/mesa/mesa-gl_%.bbappend

@@ -0,0 +1 @@
+PACKAGECONFIG:class-target = "opengl x11 gallium"

recipes-graphics/mesa/mesa_%.bbappend

@@ -0,0 +1,5 @@
+# Enable lima and panfrost Mesa drivers
+PACKAGECONFIG:append:use-mailine-graphics = " lima panfrost"
+# Enable KMS renderonly Mesa support
+# See https://cgit.freedesktop.org/mesa/mesa/commit/?id=2b780fe89300199f2334539aa1678e9b68f0434f
+GALLIUMDRIVERS:append:use-mailine-graphics = ",kmsro"

recipes-graphics/tslib/tslib/0001-Support-reading-coordinates-from-multitouch-devices.patch

@@ -1,79 +0,0 @@
-From c525c0b5d8eada982c99442454fcf7b8364e10b3 Mon Sep 17 00:00:00 2001
-From: Florian Boor <florian@kernelconcepts.de>
-Date: Fri, 1 Apr 2011 23:30:21 +0200
-Subject: [PATCH] Support reading coordinates from multitouch devices.
-
-Signed-off-by: Florian Boor <florian@kernelconcepts.de>
-Signed-off-by: Christopher Larson <kergoth@gmail.com>
----
- plugins/input-raw.c | 33 +++++++++++++++++++++++----------
- 1 file changed, 23 insertions(+), 10 deletions(-)
-
-diff --git a/plugins/input-raw.c b/plugins/input-raw.c
-index 4396eab..1e48505 100644
---- a/plugins/input-raw.c
-+++ b/plugins/input-raw.c
-@@ -40,6 +40,11 @@
- # define KEY_CNT (KEY_MAX+1)
- #endif
- 
-+#ifndef ABS_MT_POSITION_X
-+# define ABS_MT_POSITION_X       0x35    /* Center X ellipse position */
-+# define ABS_MT_POSITION_Y       0x36    /* Center Y ellipse position */
-+#endif
-+
- #include "tslib-private.h"
- 
- #define GRAB_EVENTS_WANTED	1
-@@ -160,16 +165,17 @@ static int ts_input_read(struct tslib_module_info *inf,
- 				}
- 				break;
- 			case EV_SYN:
--				/* Fill out a new complete event */
--				if (pen_up) {
--					samp->x = 0;
--					samp->y = 0;
--					samp->pressure = 0;
--					pen_up = 0;
--				} else {
--					samp->x = i->current_x;
--					samp->y = i->current_y;
--					samp->pressure = i->current_p;
-+				if (ev.code == SYN_REPORT) {
-+					/* Fill out a new complete event */
-+					if (pen_up) {
-+						samp->x = 0;
-+						samp->y = 0;
-+						samp->pressure = 0;
-+						pen_up = 0;
-+					} else {
-+						samp->x = i->current_x;
-+						samp->y = i->current_y;
-+						samp->pressure = i->current_p;
- 				}
- 				samp->tv = ev.time;
- 	#ifdef DEBUG
-@@ -179,6 +185,7 @@ static int ts_input_read(struct tslib_module_info *inf,
- 	#endif /* DEBUG */
- 				samp++;
- 				total++;
-+				}
- 				break;
- 			case EV_ABS:
- 				switch (ev.code) {
-@@ -188,6 +195,12 @@ static int ts_input_read(struct tslib_module_info *inf,
- 				case ABS_Y:
- 					i->current_y = ev.value;
- 					break;
-+				case ABS_MT_POSITION_X:
-+					i->current_x = ev.value;
-+					break;
-+				case ABS_MT_POSITION_Y:
-+					i->current_y = ev.value;
-+					break;
- 				case ABS_PRESSURE:
- 					i->current_p = ev.value;
- 					break;
--- 
-1.8.1.4
-

recipes-graphics/tslib/tslib_1.1.bbappend

@@ -1,4 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
-
-SRC_URI += "file://tslib.patch"
-

recipes-graphics/tslib/tslib_1.1.bbappend.disabled

@@ -0,0 +1,4 @@
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
+
+SRC_URI += "file://tslib.patch"
+

recipes-graphics/xorg-xserver/libdri2_git.bb

@@ -1,15 +1,15 @@
 DESCRIPTION = "Library for the DRI2 extension to the X Window System"
 
-LICENSE = "MIT-X"
+LICENSE = "MIT-CMU"
 LIC_FILES_CHKSUM = "file://COPYING;md5=827da9afab1f727f2a66574629e0f39c"
 
-DEPENDS = "libdrm libxext xextproto libxfixes dri2proto"
+DEPENDS = "libdrm libxext libxfixes xorgproto"
 
 PE = "1"
 PV = "1.0.0+git${SRCPV}"
 SRC_URI = "git://github.com/robclark/libdri2.git;protocol=http;branch=master"
 
-SRCREV_pn-${PN} = "4f1eef3183df2b270c3d5cbef07343ee5127a6a4"
+SRCREV = "4f1eef3183df2b270c3d5cbef07343ee5127a6a4"
 
 S = "${WORKDIR}/git"
 

recipes-graphics/xorg-xserver/xf86-video-fbturbo_git.bb

@@ -2,14 +2,14 @@ require recipes-graphics/xorg-driver/xorg-driver-video.inc
 
 DESCRIPTION = "X.Org X server -- A10/A13 display driver"
 
-LICENSE = "MIT-X"
+LICENSE = "MIT-CMU"
 LIC_FILES_CHKSUM = "file://COPYING;md5=f91dc3ee5ce59eb4b528e67e98a31266"
 
-DEPENDS += "sunxi-mali libump xf86driproto"
+DEPENDS += "sunxi-mali libump xorgproto"
 
 PE = "3"
 PV = "0.5.1+git${SRCPV}"
-SRCREV_pn-${PN} = "e094e3c8f9004ca3347694bd05b99d136e8621b9"
+SRCREV = "e094e3c8f9004ca3347694bd05b99d136e8621b9"
 
 SRC_URI = "git://github.com/ssvb/xf86-video-fbturbo.git;protocol=http;branch=master \
            file://20-fbturbo.conf"
@@ -18,9 +18,9 @@ S = "${WORKDIR}/git"
 
 CFLAGS += " -I${STAGING_INCDIR}/xorg "
 
-do_install_append() {
+do_install:append() {
     install -d ${D}${datadir}/X11/xorg.conf.d
     install -m 0644 ${WORKDIR}/20-fbturbo.conf ${D}${datadir}/X11/xorg.conf.d
 }
 
-FILES_${PN} += "${datadir}/X11/xorg.conf.d/20-fbturbo.conf"
+FILES:${PN} += "${datadir}/X11/xorg.conf.d/20-fbturbo.conf"

recipes-graphics/xorg-xserver/xserver-xf86-config_0.1.bbappend

@@ -1 +1 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"

recipes-graphics/xorg-xserver/xserver-xorg_%.bbappend

@@ -0,0 +1 @@
+DEPENDS += "libxshmfence"

recipes-kernel/linux-firmware/linux-firmware_%.bbappend

@@ -0,0 +1,13 @@
+# The brcmfmac driver looks for NVRAM files using the first entry in board
+# compatible since kernel >= 5.0:
+# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0ad4b55b2f29784f93875e6231bf57cd233624a2
+# We create a link to the AP6212 module NVRAM file so that firmware is
+# autodetected by the driver.
+# WARNING: The following commit is required for NVRAM files to be included in
+# linux-firmware-bcm43430 package:
+# http://git.openembedded.org/openembedded-core/commit/?id=dde0f79f32fa6bab045ef60199903f74c4cc3393
+do_install:append() {
+	ln -sf -r ${D}${nonarch_base_libdir}/firmware/brcm/brcmfmac43430-sdio.AP6212.txt ${D}${nonarch_base_libdir}/firmware/brcm/brcmfmac43430-sdio.xunlong,orangepi-zero-plus2.txt
+	ln -sf -r ${D}${nonarch_base_libdir}/firmware/brcm/brcmfmac43430-sdio.AP6212.txt ${D}${nonarch_base_libdir}/firmware/brcm/brcmfmac43430-sdio.xunlong,orangepi-zero-plus2-h3.txt
+	ln -sf -r ${D}${nonarch_base_libdir}/firmware/brcm/brcmfmac43430-sdio.AP6212.txt ${D}${nonarch_base_libdir}/firmware/brcm/brcmfmac43430-sdio.friendlyarm,nanopi-neo-plus2.txt
+}

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0001-Input-axp20x-pek-allow-wakeup-after-shutdown.patch

@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: [PATCH] Input: axp20x-pek - allow wakeup after shutdown
+
+While the AXP20x PMIC handles the power button itself after shutting
+down, it is not always possible to use the PMIC's built-in shutdown
+feature, such as when other wakeup sources are needed (for example, an
+IR remote or wake-on-LAN) that require firmware support. In that case,
+the PMIC remains on, but suspended, until the board is powered back on.
+
+During this "fake" off state, IRQ configuration is similar to system
+sleep, where enable_irq_wake() must be call on an IRQ for it to be
+wakeup capable. Run the suspend callback to arm the power button IRQs
+during the shutdown process, so the power button works in this state.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/input/misc/axp20x-pek.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/input/misc/axp20x-pek.c
++++ b/drivers/input/misc/axp20x-pek.c
+@@ -354,7 +354,7 @@ static int axp20x_pek_probe(struct platf
+ 	return 0;
+ }
+ 
+-static int __maybe_unused axp20x_pek_suspend(struct device *dev)
++static int axp20x_pek_suspend(struct device *dev)
+ {
+ 	struct axp20x_pek *axp20x_pek = dev_get_drvdata(dev);
+ 
+@@ -413,6 +413,11 @@ static const struct dev_pm_ops axp20x_pe
+ #endif
+ };
+ 
++static void axp20x_pek_shutdown(struct platform_device *pdev)
++{
++	axp20x_pek_suspend(&pdev->dev);
++}
++
+ static const struct platform_device_id axp_pek_id_match[] = {
+ 	{
+ 		.name = "axp20x-pek",
+@@ -428,6 +433,7 @@ MODULE_DEVICE_TABLE(platform, axp_pek_id
+ 
+ static struct platform_driver axp20x_pek_driver = {
+ 	.probe		= axp20x_pek_probe,
++	.shutdown	= axp20x_pek_shutdown,
+ 	.id_table	= axp_pek_id_match,
+ 	.driver		= {
+ 		.name		= "axp20x-pek",

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0002-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch

@@ -0,0 +1,197 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 29 Dec 2019 20:23:28 -0600
+Subject: [PATCH] clk: Implement protected-clocks for all OF clock providers
+
+This is a generic implementation of the "protected-clocks" property from
+the common clock binding. It allows firmware to inform the OS about
+clocks that must not be disabled while the OS is running.
+
+This implementation comes with some caveats:
+
+1) Clocks that have CLK_IS_CRITICAL in their init data are prepared/
+enabled before they are attached to the clock tree. protected-clocks are
+only protected once the clock provider is added, which is generally
+after all of the clocks it provides have been registered. This leaves a
+window of opportunity where something could disable or modify the clock,
+such as a driver running on another CPU, or the clock core itself. There
+is a comment to this effect in __clk_core_init():
+
+  /*
+   * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
+   * don't get accidentally disabled when walking the orphan tree and
+   * reparenting clocks
+   */
+
+Similarly, these clocks will be enabled after they are first reparented,
+unlike other CLK_IS_CRITICAL clocks. See the comment in
+clk_core_reparent_orphans_nolock():
+
+  /*
+   * We need to use __clk_set_parent_before() and _after() to
+   * to properly migrate any prepare/enable count of the orphan
+   * clock. This is important for CLK_IS_CRITICAL clocks, which
+   * are enabled during init but might not have a parent yet.
+   */
+
+Ideally we could detect protected clocks before they are reparented, but
+there are two problems with that:
+
+  a) From the clock core's perspective, hw->init is const.
+
+  b) The clock core doesn't see the device_node until __clk_register is
+     called on the first clock.
+
+So the only "race-free" way to detect protected-clocks is to do it in
+the middle of __clk_register, between when core->flags is initialized
+and calling __clk_core_init(). That requires scanning the device tree
+again for each clock, which is part of why I didn't do it that way.
+
+2) __clk_protect needs to be idempotent, for two reasons:
+
+  a) Clocks with CLK_IS_CRITICAL in their init data are already
+     prepared/enabled, and we don't want to prepare/enable them again.
+
+  b) of_clk_set_defaults() is called twice for (at least some) clock
+     controllers registered with CLK_OF_DECLARE. It is called first in
+     of_clk_add_provider()/of_clk_add_hw_provider() inside clk_init_cb,
+     and again afterward in of_clk_init(). The second call in
+     of_clk_init() may be unnecessary, but verifying that would require
+     auditing all users of CLK_OF_DECLARE to ensure they called one of
+     the of_clk_add{,_hw}_provider functions.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/clk-conf.c | 54 ++++++++++++++++++++++++++++++++++++++++++
+ drivers/clk/clk.c      | 31 ++++++++++++++++++++++++
+ drivers/clk/clk.h      |  2 ++
+ 3 files changed, 87 insertions(+)
+
+--- a/drivers/clk/clk-conf.c
++++ b/drivers/clk/clk-conf.c
+@@ -11,6 +11,54 @@
+ #include <linux/of.h>
+ #include <linux/printk.h>
+ 
++#include "clk.h"
++
++static int __set_clk_flags(struct device_node *node)
++{
++	struct of_phandle_args clkspec;
++	struct property *prop;
++	int i, index = 0, rc;
++	const __be32 *cur;
++	struct clk *clk;
++	u32 nr_cells;
++
++	rc = of_property_read_u32(node, "#clock-cells", &nr_cells);
++	if (rc < 0) {
++		pr_err("clk: missing #clock-cells property on %pOF\n", node);
++		return rc;
++	}
++
++	clkspec.np         = node;
++	clkspec.args_count = nr_cells;
++
++	of_property_for_each_u32(node, "protected-clocks", prop, cur, clkspec.args[0]) {
++		/* read the remainder of the clock specifier */
++		for (i = 1; i < nr_cells; ++i) {
++			cur = of_prop_next_u32(prop, cur, &clkspec.args[i]);
++			if (!cur) {
++				pr_err("clk: invalid value of protected-clocks"
++				       " property at %pOF\n", node);
++				return -EINVAL;
++			}
++		}
++		clk = of_clk_get_from_provider(&clkspec);
++		if (IS_ERR(clk)) {
++			if (PTR_ERR(clk) != -EPROBE_DEFER)
++				pr_err("clk: couldn't get protected clock"
++				       " %u for %pOF\n", index, node);
++			return PTR_ERR(clk);
++		}
++
++		rc = __clk_protect(clk);
++		if (rc < 0)
++			pr_warn("clk: failed to protect %s: %d\n",
++				__clk_get_name(clk), rc);
++		clk_put(clk);
++		index++;
++	}
++	return 0;
++}
++
+ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
+ {
+ 	struct of_phandle_args clkspec;
+@@ -135,6 +183,12 @@ int of_clk_set_defaults(struct device_no
+ 	if (!node)
+ 		return 0;
+ 
++	if (clk_supplier) {
++		rc = __set_clk_flags(node);
++		if (rc < 0)
++			return rc;
++	}
++
+ 	rc = __set_clk_parents(node, clk_supplier);
+ 	if (rc < 0)
+ 		return rc;
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -4271,6 +4271,37 @@ struct clk *devm_clk_hw_get_clk(struct d
+ EXPORT_SYMBOL_GPL(devm_clk_hw_get_clk);
+ 
+ /*
++ * clk-conf helpers
++ */
++
++int __clk_protect(struct clk *clk)
++{
++	struct clk_core *core = clk->core;
++	int ret = 0;
++
++	clk_prepare_lock();
++
++	/*
++	 * If CLK_IS_CRITICAL was set in the clock's init data, then
++	 * the clock was already prepared/enabled when it was added.
++	 */
++	if (core->flags & CLK_IS_CRITICAL)
++		goto out;
++
++	core->flags |= CLK_IS_CRITICAL;
++	ret = clk_core_prepare(core);
++	if (ret)
++		goto out;
++
++	ret = clk_core_enable_lock(core);
++
++out:
++	clk_prepare_unlock();
++
++	return ret;
++}
++
++/*
+  * clkdev helpers
+  */
+ 
+--- a/drivers/clk/clk.h
++++ b/drivers/clk/clk.h
+@@ -24,6 +24,7 @@ struct clk_hw *clk_find_hw(const char *d
+ #ifdef CONFIG_COMMON_CLK
+ struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
+ 			      const char *dev_id, const char *con_id);
++int __clk_protect(struct clk *clk);
+ void __clk_put(struct clk *clk);
+ #else
+ /* All these casts to avoid ifdefs in clkdev... */
+@@ -33,6 +34,7 @@ clk_hw_create_clk(struct device *dev, st
+ {
+ 	return (struct clk *)hw;
+ }
++static inline int __clk_protect(struct clk *clk) { return 0; }
+ static inline void __clk_put(struct clk *clk) { }
+ 
+ #endif

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0003-Revert-clk-qcom-Support-protected-clocks-property.patch

@@ -0,0 +1,49 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 30 Dec 2019 12:39:31 -0600
+Subject: [PATCH] Revert "clk: qcom: Support 'protected-clocks' property"
+
+Now that protected-clocks is handled in the clk core, this
+driver-specific implementation is redundant.
+
+This reverts commit b181b3b801da8893c8eb706e448dd5111b02de60.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/qcom/common.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+--- a/drivers/clk/qcom/common.c
++++ b/drivers/clk/qcom/common.c
+@@ -194,22 +194,6 @@ int qcom_cc_register_sleep_clk(struct de
+ }
+ EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
+ 
+-/* Drop 'protected-clocks' from the list of clocks to register */
+-static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
+-{
+-	struct device_node *np = dev->of_node;
+-	struct property *prop;
+-	const __be32 *p;
+-	u32 i;
+-
+-	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
+-		if (i >= cc->num_rclks)
+-			continue;
+-
+-		cc->rclks[i] = NULL;
+-	}
+-}
+-
+ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
+ 					 void *data)
+ {
+@@ -272,8 +256,6 @@ int qcom_cc_really_probe(struct platform
+ 	cc->rclks = rclks;
+ 	cc->num_rclks = num_clks;
+ 
+-	qcom_cc_drop_protected(dev, cc);
+-
+ 	for (i = 0; i < num_clk_hws; i++) {
+ 		ret = devm_clk_hw_register(dev, clk_hws[i]);
+ 		if (ret)

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0007-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch

@@ -0,0 +1,62 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: [PATCH] rtc: sun6i: Allow RTC wakeup after shutdown
+
+Only IRQs that have enable_irq_wake() called on them can wake the system
+from sleep or after it has been shut down. Currently, the RTC alarm can
+only wake the system from sleep. Run the suspend callback to arm the IRQ
+during the shutdown process, so the RTC alarm also works after shutdown.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/rtc/rtc-sun6i.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -641,7 +641,6 @@ static const struct rtc_class_ops sun6i_
+ 	.alarm_irq_enable	= sun6i_rtc_alarm_irq_enable
+ };
+ 
+-#ifdef CONFIG_PM_SLEEP
+ /* Enable IRQ wake on suspend, to wake up from RTC. */
+ static int sun6i_rtc_suspend(struct device *dev)
+ {
+@@ -654,7 +653,7 @@ static int sun6i_rtc_suspend(struct devi
+ }
+ 
+ /* Disable IRQ wake on resume. */
+-static int sun6i_rtc_resume(struct device *dev)
++static int __maybe_unused sun6i_rtc_resume(struct device *dev)
+ {
+ 	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ 
+@@ -663,7 +662,6 @@ static int sun6i_rtc_resume(struct devic
+ 
+ 	return 0;
+ }
+-#endif
+ 
+ static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
+ 	sun6i_rtc_suspend, sun6i_rtc_resume);
+@@ -735,6 +733,11 @@ static int sun6i_rtc_probe(struct platfo
+ 	return 0;
+ }
+ 
++static void sun6i_rtc_shutdown(struct platform_device *pdev)
++{
++	sun6i_rtc_suspend(&pdev->dev);
++}
++
+ /*
+  * As far as RTC functionality goes, all models are the same. The
+  * datasheets claim that different models have different number of
+@@ -755,6 +758,7 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids
+ 
+ static struct platform_driver sun6i_rtc_driver = {
+ 	.probe		= sun6i_rtc_probe,
++	.shutdown	= sun6i_rtc_shutdown,
+ 	.driver		= {
+ 		.name		= "sun6i-rtc",
+ 		.of_match_table = sun6i_rtc_dt_ids,

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch

@@ -0,0 +1,122 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 5 Mar 2019 22:02:41 -0600
+Subject: [PATCH] firmware: arm_scpi: Support unidirectional mailbox channels
+
+Some mailbox controllers have only unidirectional channels, so we need a
+pair of them for each SCPI channel. If a mbox-names property is present,
+look for "rx" and "tx" mbox channels; otherwise, the existing behavior
+is preserved, and a single mbox channel is used for each SCPI channel.
+
+Note that since the mailbox framework only supports a single phandle
+with each name (mbox_request_channel_byname always returns the first
+one), this new mode only supports a single SCPI channel.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/firmware/arm_scpi.c | 58 +++++++++++++++++++++++++++++--------
+ 1 file changed, 46 insertions(+), 12 deletions(-)
+
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -231,7 +231,8 @@ struct scpi_xfer {
+ 
+ struct scpi_chan {
+ 	struct mbox_client cl;
+-	struct mbox_chan *chan;
++	struct mbox_chan *rx_chan;
++	struct mbox_chan *tx_chan;
+ 	void __iomem *tx_payload;
+ 	void __iomem *rx_payload;
+ 	struct list_head rx_pending;
+@@ -505,7 +506,7 @@ static int scpi_send_message(u8 idx, voi
+ 	msg->rx_len = rx_len;
+ 	reinit_completion(&msg->done);
+ 
+-	ret = mbox_send_message(scpi_chan->chan, msg);
++	ret = mbox_send_message(scpi_chan->tx_chan, msg);
+ 	if (ret < 0 || !rx_buf)
+ 		goto out;
+ 
+@@ -856,8 +857,13 @@ static void scpi_free_channels(void *dat
+ 	struct scpi_drvinfo *info = data;
+ 	int i;
+ 
+-	for (i = 0; i < info->num_chans; i++)
+-		mbox_free_channel(info->channels[i].chan);
++	for (i = 0; i < info->num_chans; i++) {
++		struct scpi_chan *pchan = &info->channels[i];
++
++		if (pchan->tx_chan != pchan->rx_chan)
++			mbox_free_channel(pchan->tx_chan);
++		mbox_free_channel(pchan->rx_chan);
++	}
+ }
+ 
+ static int scpi_remove(struct platform_device *pdev)
+@@ -913,6 +919,7 @@ static int scpi_probe(struct platform_de
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct scpi_drvinfo *scpi_drvinfo;
++	bool use_mbox_names = false;
+ 
+ 	scpi_drvinfo = devm_kzalloc(dev, sizeof(*scpi_drvinfo), GFP_KERNEL);
+ 	if (!scpi_drvinfo)
+@@ -926,6 +933,14 @@ static int scpi_probe(struct platform_de
+ 		dev_err(dev, "no mboxes property in '%pOF'\n", np);
+ 		return -ENODEV;
+ 	}
++	if (of_get_property(dev->of_node, "mbox-names", NULL)) {
++		use_mbox_names = true;
++		if (count != 2) {
++			dev_err(dev, "need exactly 2 mboxes with mbox-names\n");
++			return -ENODEV;
++		}
++		count /= 2;
++	}
+ 
+ 	scpi_info->channels = devm_kcalloc(dev, count, sizeof(struct scpi_chan),
+ 					   GFP_KERNEL);
+@@ -974,15 +989,34 @@ static int scpi_probe(struct platform_de
+ 		mutex_init(&pchan->xfers_lock);
+ 
+ 		ret = scpi_alloc_xfer_list(dev, pchan);
+-		if (!ret) {
+-			pchan->chan = mbox_request_channel(cl, idx);
+-			if (!IS_ERR(pchan->chan))
+-				continue;
+-			ret = PTR_ERR(pchan->chan);
+-			if (ret != -EPROBE_DEFER)
+-				dev_err(dev, "failed to get channel%d err %d\n",
+-					idx, ret);
++		if (ret)
++			return ret;
++
++		if (use_mbox_names) {
++			pchan->rx_chan = mbox_request_channel_byname(cl, "rx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = mbox_request_channel_byname(cl, "tx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->tx_chan);
++				goto fail;
++			}
++		} else {
++			pchan->rx_chan = mbox_request_channel(cl, idx);
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = pchan->rx_chan;
+ 		}
++		continue;
++
++fail:
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "failed to get channel%d err %d\n",
++				idx, ret);
+ 		return ret;
+ 	}
+ 

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0012-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch

@@ -0,0 +1,46 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 14 Dec 2019 20:54:40 -0600
+Subject: [PATCH] arm64: dts: allwinner: h6: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -88,6 +88,13 @@
+ 		method = "smc";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -196,6 +203,19 @@
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@100000 {
++				compatible = "mmio-sram";
++				reg = <0x00100000 0x18000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00100000 0x18000>;
++
++				scpi_sram: scpi-sram@17c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x17c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@28000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00028000 0x1e000>;

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0013-ASoC-hdmi-codec-fix-channel-allocation.patch

@@ -0,0 +1,142 @@
+From 91b69779e0875e58d8973b2938a1cc4b7a1c455b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 25 Mar 2018 22:17:06 +0200
+Subject: [PATCH 22/44] ASoC: hdmi-codec: fix channel allocation
+
+---
+ sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------
+ 1 file changed, 52 insertions(+), 61 deletions(-)
+
+--- a/sound/soc/codecs/hdmi-codec.c
++++ b/sound/soc/codecs/hdmi-codec.c
+@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem h
+  */
+ static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
+ 	{ .ca_id = 0x00, .n_ch = 2,
+-	  .mask = FL | FR},
+-	/* 2.1 */
+-	{ .ca_id = 0x01, .n_ch = 4,
+-	  .mask = FL | FR | LFE},
+-	/* Dolby Surround */
++	  .mask = FL | FR },
++	{ .ca_id = 0x03, .n_ch = 4,
++	  .mask = FL | FR | LFE | FC },
+ 	{ .ca_id = 0x02, .n_ch = 4,
+ 	  .mask = FL | FR | FC },
+-	/* surround51 */
++	{ .ca_id = 0x01, .n_ch = 4,
++	  .mask = FL | FR | LFE },
+ 	{ .ca_id = 0x0b, .n_ch = 6,
+-	  .mask = FL | FR | LFE | FC | RL | RR},
+-	/* surround40 */
+-	{ .ca_id = 0x08, .n_ch = 6,
+-	  .mask = FL | FR | RL | RR },
+-	/* surround41 */
+-	{ .ca_id = 0x09, .n_ch = 6,
+-	  .mask = FL | FR | LFE | RL | RR },
+-	/* surround50 */
++	  .mask = FL | FR | LFE | FC | RL | RR },
+ 	{ .ca_id = 0x0a, .n_ch = 6,
+ 	  .mask = FL | FR | FC | RL | RR },
+-	/* 6.1 */
+-	{ .ca_id = 0x0f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | RC },
+-	/* surround71 */
++	{ .ca_id = 0x09, .n_ch = 6,
++	  .mask = FL | FR | LFE | RL | RR },
++	{ .ca_id = 0x08, .n_ch = 6,
++	  .mask = FL | FR | RL | RR },
++	{ .ca_id = 0x07, .n_ch = 6,
++	  .mask = FL | FR | LFE | FC | RC },
++	{ .ca_id = 0x06, .n_ch = 6,
++	  .mask = FL | FR | FC | RC },
++	{ .ca_id = 0x05, .n_ch = 6,
++	  .mask = FL | FR | LFE | RC },
++	{ .ca_id = 0x04, .n_ch = 6,
++	  .mask = FL | FR | RC },
+ 	{ .ca_id = 0x13, .n_ch = 8,
+ 	  .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
+-	/* others */
+-	{ .ca_id = 0x03, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC },
+-	{ .ca_id = 0x04, .n_ch = 8,
+-	  .mask = FL | FR | RC},
+-	{ .ca_id = 0x05, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC },
+-	{ .ca_id = 0x06, .n_ch = 8,
+-	  .mask = FL | FR | FC | RC },
+-	{ .ca_id = 0x07, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RC },
+-	{ .ca_id = 0x0c, .n_ch = 8,
+-	  .mask = FL | FR | RC | RL | RR },
+-	{ .ca_id = 0x0d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RC },
+-	{ .ca_id = 0x0e, .n_ch = 8,
+-	  .mask = FL | FR | FC | RL | RR | RC },
+-	{ .ca_id = 0x10, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x11, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x12, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | RLC | RRC },
+-	{ .ca_id = 0x14, .n_ch = 8,
+-	  .mask = FL | FR | FLC | FRC },
+-	{ .ca_id = 0x15, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FLC | FRC },
+-	{ .ca_id = 0x16, .n_ch = 8,
+-	  .mask = FL | FR | FC | FLC | FRC },
+-	{ .ca_id = 0x17, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | FLC | FRC },
+-	{ .ca_id = 0x18, .n_ch = 8,
+-	  .mask = FL | FR | RC | FLC | FRC },
+-	{ .ca_id = 0x19, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FLC | FRC },
+-	{ .ca_id = 0x1a, .n_ch = 8,
+-	  .mask = FL | FR | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1b, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
+-	{ .ca_id = 0x1c, .n_ch = 8,
+-	  .mask = FL | FR | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1d, .n_ch = 8,
+-	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
+ 	{ .ca_id = 0x1e, .n_ch = 8,
+ 	  .mask = FL | FR | FC | RL | RR | FLC | FRC },
+-	{ .ca_id = 0x1f, .n_ch = 8,
+-	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
++	{ .ca_id = 0x11, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
++	{ .ca_id = 0x10, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | RLC | RRC },
++	{ .ca_id = 0x1c, .n_ch = 8,
++	  .mask = FL | FR | RL | RR | FLC | FRC },
++	{ .ca_id = 0x0f, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | RL | RR | RC },
++	{ .ca_id = 0x1b, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0e, .n_ch = 8,
++	  .mask = FL | FR | FC | RL | RR | RC },
++	{ .ca_id = 0x1a, .n_ch = 8,
++	  .mask = FL | FR | RC | FC | FLC | FRC },
++	{ .ca_id = 0x0d, .n_ch = 8,
++	  .mask = FL | FR | LFE | RL | RR | RC },
++	{ .ca_id = 0x19, .n_ch = 8,
++	  .mask = FL | FR | LFE | RC | FLC | FRC },
++	{ .ca_id = 0x0c, .n_ch = 8,
++	  .mask = FL | FR | RC | RL | RR },
++	{ .ca_id = 0x18, .n_ch = 8,
++	  .mask = FL | FR | RC | FLC | FRC },
++	{ .ca_id = 0x17, .n_ch = 8,
++	  .mask = FL | FR | LFE | FC | FLC | FRC },
++	{ .ca_id = 0x16, .n_ch = 8,
++	  .mask = FL | FR | FC | FLC | FRC },
++	{ .ca_id = 0x15, .n_ch = 8,
++	  .mask = FL | FR | LFE | FLC | FRC },
++	{ .ca_id = 0x14, .n_ch = 8,
++	  .mask = FL | FR | FLC | FRC },
+ };
+ 
+ struct hdmi_codec_priv {

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0028-mfd-Add-support-for-AC200.patch

@@ -0,0 +1,406 @@
+From 59adceb6f34521c0f1a229f20ee9961269daa539 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:21 +0200
+Subject: [PATCH 38/44] mfd: Add support for AC200
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/mfd/Kconfig       |   9 ++
+ drivers/mfd/Makefile      |   1 +
+ drivers/mfd/ac200.c       | 150 +++++++++++++++++++++++++++
+ include/linux/mfd/ac200.h | 209 ++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 369 insertions(+)
+ create mode 100644 drivers/mfd/ac200.c
+ create mode 100644 include/linux/mfd/ac200.h
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -178,6 +178,15 @@ config MFD_AC100
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like codecs or RTC under the corresponding menus.
+ 
++config MFD_AC200
++	tristate "X-Powers AC200"
++	select MFD_CORE
++	depends on I2C
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or RTC under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -142,6 +142,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-s
+ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
++obj-$(CONFIG_MFD_AC200)		+= ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+--- /dev/null
++++ b/drivers/mfd/ac200.c
+@@ -0,0 +1,148 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ *
++ * Based on AC100 driver with following copyrights:
++ * Copyright (2016) Chen-Yu Tsai
++ */
++
++#include <linux/i2c.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ac200.h>
++#include <linux/module.h>
++#include <linux/of.h>
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_min = AC200_SYS_VERSION,
++		.range_max = AC200_IC_CHARA1,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.reg_bits	= 8,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_IC_CHARA1,
++};
++
++static struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-codec",
++		.of_compatible	= "x-powers,ac200-codec",
++	}, {
++		.name		= "ac200-efuse",
++		.of_compatible	= "x-powers,ac200-efuse",
++	}, {
++		.name		= "ac200-ephy",
++		.of_compatible	= "x-powers,ac200-ephy",
++	}, {
++		.name		= "ac200-rtc",
++		.of_compatible	= "x-powers,ac200-rtc",
++	}, {
++		.name		= "ac200-tve",
++		.of_compatible	= "x-powers,ac200-tve",
++	},
++};
++
++static int ac200_i2c_probe(struct i2c_client *i2c,
++			   const struct i2c_device_id *id)
++{
++	struct device *dev = &i2c->dev;
++	struct ac200_dev *ac200;
++	int ret;
++
++	ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++	if (!ac200)
++		return -ENOMEM;
++
++	i2c_set_clientdata(i2c, ac200);
++
++	ac200->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(ac200->clk)) {
++		ret = PTR_ERR(ac200->clk);
++		dev_err(dev, "Can't obtain the clock: %d\n", ret);
++		return ret;
++	}
++
++	ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++	if (IS_ERR(ac200->regmap)) {
++		ret = PTR_ERR(ac200->regmap);
++		dev_err(dev, "Regmap init failed: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(ac200->clk);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++	if (ret)
++		goto err;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	if (ret)
++		goto err;
++
++	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++				   ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(dev, "Failed to add MFD devices: %d\n", ret);
++		goto err;
++	}
++
++	return 0;
++
++err:
++	clk_disable_unprepare(ac200->clk);
++	return ret;
++}
++
++void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	clk_disable_unprepare(ac200->clk);
++}
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/linux/mfd/ac200.h
+@@ -0,0 +1,209 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * AC200 register list
++ *
++ * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#ifndef __LINUX_MFD_AC200_H
++#define __LINUX_MFD_AC200_H
++
++#include <linux/clk.h>
++#include <linux/regmap.h>
++
++/* interface registers (can be accessed from any page) */
++#define AC200_TWI_CHANGE_TO_RSB		0x3E
++#define AC200_TWI_PAD_DELAY		0xC4
++#define AC200_TWI_REG_ADDR_H		0xFE
++
++/* General registers */
++#define AC200_SYS_VERSION		0x0000
++#define AC200_SYS_CONTROL		0x0002
++#define AC200_SYS_IRQ_ENABLE		0x0004
++#define AC200_SYS_IRQ_STATUS		0x0006
++#define AC200_SYS_CLK_CTL		0x0008
++#define AC200_SYS_DLDO_OSC_CTL		0x000A
++#define AC200_SYS_PLL_CTL0		0x000C
++#define AC200_SYS_PLL_CTL1		0x000E
++#define AC200_SYS_AUDIO_CTL0		0x0010
++#define AC200_SYS_AUDIO_CTL1		0x0012
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_SYS_TVE_CTL0		0x0018
++#define AC200_SYS_TVE_CTL1		0x001A
++
++/* Audio Codec registers */
++#define AC200_AC_SYS_CLK_CTL		0x2000
++#define AC200_SYS_MOD_RST		0x2002
++#define AC200_SYS_SAMP_CTL		0x2004
++#define AC200_I2S_CTL			0x2100
++#define AC200_I2S_CLK			0x2102
++#define AC200_I2S_FMT0			0x2104
++#define AC200_I2S_FMT1			0x2108
++#define AC200_I2S_MIX_SRC		0x2114
++#define AC200_I2S_MIX_GAIN		0x2116
++#define AC200_I2S_DACDAT_DVC		0x2118
++#define AC200_I2S_ADCDAT_DVC		0x211A
++#define AC200_AC_DAC_DPC		0x2200
++#define AC200_AC_DAC_MIX_SRC		0x2202
++#define AC200_AC_DAC_MIX_GAIN		0x2204
++#define AC200_DACA_OMIXER_CTRL		0x2220
++#define AC200_OMIXER_SR			0x2222
++#define AC200_LINEOUT_CTRL		0x2224
++#define AC200_AC_ADC_DPC		0x2300
++#define AC200_MBIAS_CTRL		0x2310
++#define AC200_ADC_MIC_CTRL		0x2320
++#define AC200_ADCMIXER_SR		0x2322
++#define AC200_ANALOG_TUNING0		0x232A
++#define AC200_ANALOG_TUNING1		0x232C
++#define AC200_AC_AGC_SEL		0x2480
++#define AC200_ADC_DAPLCTRL		0x2500
++#define AC200_ADC_DAPRCTRL		0x2502
++#define AC200_ADC_DAPLSTA		0x2504
++#define AC200_ADC_DAPRSTA		0x2506
++#define AC200_ADC_DAPLTL		0x2508
++#define AC200_ADC_DAPRTL		0x250A
++#define AC200_ADC_DAPLHAC		0x250C
++#define AC200_ADC_DAPLLAC		0x250E
++#define AC200_ADC_DAPRHAC		0x2510
++#define AC200_ADC_DAPRLAC		0x2512
++#define AC200_ADC_DAPLDT		0x2514
++#define AC200_ADC_DAPLAT		0x2516
++#define AC200_ADC_DAPRDT		0x2518
++#define AC200_ADC_DAPRAT		0x251A
++#define AC200_ADC_DAPNTH		0x251C
++#define AC200_ADC_DAPLHNAC		0x251E
++#define AC200_ADC_DAPLLNAC		0x2520
++#define AC200_ADC_DAPRHNAC		0x2522
++#define AC200_ADC_DAPRLNAC		0x2524
++#define AC200_AC_DAPHHPFC		0x2526
++#define AC200_AC_DAPLHPFC		0x2528
++#define AC200_AC_DAPOPT			0x252A
++#define AC200_AC_DAC_DAPCTRL		0x3000
++#define AC200_AC_DRC_HHPFC		0x3002
++#define AC200_AC_DRC_LHPFC		0x3004
++#define AC200_AC_DRC_CTRL		0x3006
++#define AC200_AC_DRC_LPFHAT		0x3008
++#define AC200_AC_DRC_LPFLAT		0x300A
++#define AC200_AC_DRC_RPFHAT		0x300C
++#define AC200_AC_DRC_RPFLAT		0x300E
++#define AC200_AC_DRC_LPFHRT		0x3010
++#define AC200_AC_DRC_LPFLRT		0x3012
++#define AC200_AC_DRC_RPFHRT		0x3014
++#define AC200_AC_DRC_RPFLRT		0x3016
++#define AC200_AC_DRC_LRMSHAT		0x3018
++#define AC200_AC_DRC_LRMSLAT		0x301A
++#define AC200_AC_DRC_RRMSHAT		0x301C
++#define AC200_AC_DRC_RRMSLAT		0x301E
++#define AC200_AC_DRC_HCT		0x3020
++#define AC200_AC_DRC_LCT		0x3022
++#define AC200_AC_DRC_HKC		0x3024
++#define AC200_AC_DRC_LKC		0x3026
++#define AC200_AC_DRC_HOPC		0x3028
++#define AC200_AC_DRC_LOPC		0x302A
++#define AC200_AC_DRC_HLT		0x302C
++#define AC200_AC_DRC_LLT		0x302E
++#define AC200_AC_DRC_HKI		0x3030
++#define AC200_AC_DRC_LKI		0x3032
++#define AC200_AC_DRC_HOPL		0x3034
++#define AC200_AC_DRC_LOPL		0x3036
++#define AC200_AC_DRC_HET		0x3038
++#define AC200_AC_DRC_LET		0x303A
++#define AC200_AC_DRC_HKE		0x303C
++#define AC200_AC_DRC_LKE		0x303E
++#define AC200_AC_DRC_HOPE		0x3040
++#define AC200_AC_DRC_LOPE		0x3042
++#define AC200_AC_DRC_HKN		0x3044
++#define AC200_AC_DRC_LKN		0x3046
++#define AC200_AC_DRC_SFHAT		0x3048
++#define AC200_AC_DRC_SFLAT		0x304A
++#define AC200_AC_DRC_SFHRT		0x304C
++#define AC200_AC_DRC_SFLRT		0x304E
++#define AC200_AC_DRC_MXGHS		0x3050
++#define AC200_AC_DRC_MXGLS		0x3052
++#define AC200_AC_DRC_MNGHS		0x3054
++#define AC200_AC_DRC_MNGLS		0x3056
++#define AC200_AC_DRC_EPSHC		0x3058
++#define AC200_AC_DRC_EPSLC		0x305A
++#define AC200_AC_DRC_HPFHGAIN		0x305E
++#define AC200_AC_DRC_HPFLGAIN		0x3060
++#define AC200_AC_DRC_BISTCR		0x3100
++#define AC200_AC_DRC_BISTST		0x3102
++
++/* TVE registers */
++#define AC200_TVE_CTL0			0x4000
++#define AC200_TVE_CTL1			0x4002
++#define AC200_TVE_MOD0			0x4004
++#define AC200_TVE_MOD1			0x4006
++#define AC200_TVE_DAC_CFG0		0x4008
++#define AC200_TVE_DAC_CFG1		0x400A
++#define AC200_TVE_YC_DELAY		0x400C
++#define AC200_TVE_YC_FILTER		0x400E
++#define AC200_TVE_BURST_FRQ0		0x4010
++#define AC200_TVE_BURST_FRQ1		0x4012
++#define AC200_TVE_FRONT_PORCH		0x4014
++#define AC200_TVE_BACK_PORCH		0x4016
++#define AC200_TVE_TOTAL_LINE		0x401C
++#define AC200_TVE_FIRST_ACTIVE		0x401E
++#define AC200_TVE_BLACK_LEVEL		0x4020
++#define AC200_TVE_BLANK_LEVEL		0x4022
++#define AC200_TVE_PLUG_EN		0x4030
++#define AC200_TVE_PLUG_IRQ_EN		0x4032
++#define AC200_TVE_PLUG_IRQ_STA		0x4034
++#define AC200_TVE_PLUG_STA		0x4038
++#define AC200_TVE_PLUG_DEBOUNCE		0x4040
++#define AC200_TVE_DAC_TEST		0x4042
++#define AC200_TVE_PLUG_PULSE_LEVEL	0x40F4
++#define AC200_TVE_PLUG_PULSE_START	0x40F8
++#define AC200_TVE_PLUG_PULSE_PERIOD	0x40FA
++#define AC200_TVE_IF_CTL		0x5000
++#define AC200_TVE_IF_TIM0		0x5008
++#define AC200_TVE_IF_TIM1		0x500A
++#define AC200_TVE_IF_TIM2		0x500C
++#define AC200_TVE_IF_TIM3		0x500E
++#define AC200_TVE_IF_SYNC0		0x5010
++#define AC200_TVE_IF_SYNC1		0x5012
++#define AC200_TVE_IF_SYNC2		0x5014
++#define AC200_TVE_IF_TIM4		0x5016
++#define AC200_TVE_IF_STATUS		0x5018
++
++/* EPHY registers */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_BIST			0x6002
++
++/* eFuse registers (0x8000 - 0x9FFF, layout unknown) */
++
++/* RTC registers */
++#define AC200_LOSC_CTRL0		0xA000
++#define AC200_LOSC_CTRL1		0xA002
++#define AC200_LOSC_AUTO_SWT_STA		0xA004
++#define AC200_INTOSC_CLK_PRESCAL	0xA008
++#define AC200_RTC_YY_MM_DD0		0xA010
++#define AC200_RTC_YY_MM_DD1		0xA012
++#define AC200_RTC_HH_MM_SS0		0xA014
++#define AC200_RTC_HH_MM_SS1		0xA016
++#define AC200_ALARM0_CUR_VLU0		0xA024
++#define AC200_ALARM0_CUR_VLU1		0xA026
++#define AC200_ALARM0_ENABLE		0xA028
++#define AC200_ALARM0_IRQ_EN		0xA02C
++#define AC200_ALARM0_IRQ_STA		0xA030
++#define AC200_ALARM1_WK_HH_MM_SS0	0xA040
++#define AC200_ALARM1_WK_HH_MM_SS1	0xA042
++#define AC200_ALARM1_ENABLE		0xA044
++#define AC200_ALARM1_IRQ_EN		0xA048
++#define AC200_ALARM1_IRQ_STA		0xA04C
++#define AC200_ALARM_CONFIG		0xA050
++#define AC200_LOSC_OUT_GATING		0xA060
++#define AC200_GP_DATA(x)		(0xA100 + (x) * 2)
++#define AC200_RTC_DEB			0xA170
++#define AC200_GPL_HOLD_OUTPUT		0xA180
++#define AC200_VDD_RTC			0xA190
++#define AC200_IC_CHARA0			0xA1F0
++#define AC200_IC_CHARA1			0xA1F2
++
++struct ac200_dev {
++	struct clk	*clk;
++	struct regmap	*regmap;
++};
++
++#endif /* __LINUX_MFD_AC200_H */

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0029-net-phy-Add-support-for-AC200-EPHY.patch

@@ -0,0 +1,276 @@
+From cbf68fb141747879e2e6c43584c1e1e3b4d77683 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:57 +0200
+Subject: [PATCH 39/44] net: phy: Add support for AC200 EPHY
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/net/phy/Kconfig  |   7 ++
+ drivers/net/phy/Makefile |   1 +
+ drivers/net/phy/ac200.c  | 234 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 242 insertions(+)
+ create mode 100644 drivers/net/phy/ac200.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -63,6 +63,13 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AC200_PHY
++	tristate "AC200 EPHY"
++	depends on NVMEM
++	depends on OF
++	help
++	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD PHYs"
+ 	help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -30,6 +30,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
+ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
++obj-$(CONFIG_AC200_PHY)		+= ac200.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ aquantia-objs			+= aquantia_main.o
+--- /dev/null
++++ b/drivers/net/phy/ac200.c
+@@ -0,0 +1,234 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * Driver for AC200 Ethernet PHY
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mfd/ac200.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#define AC200_EPHY_ID			0x00441400
++#define AC200_EPHY_ID_MASK		0x0ffffff0
++
++/* macros for system ephy control 0 register */
++#define AC200_EPHY_RESET_INVALID	BIT(0)
++#define AC200_EPHY_SYSCLK_GATING	BIT(1)
++
++/* macros for system ephy control 1 register */
++#define AC200_EPHY_E_EPHY_MII_IO_EN	BIT(0)
++#define AC200_EPHY_E_LNK_LED_IO_EN	BIT(1)
++#define AC200_EPHY_E_SPD_LED_IO_EN	BIT(2)
++#define AC200_EPHY_E_DPX_LED_IO_EN	BIT(3)
++
++/* macros for ephy control register */
++#define AC200_EPHY_SHUTDOWN		BIT(0)
++#define AC200_EPHY_LED_POL		BIT(1)
++#define AC200_EPHY_CLK_SEL		BIT(2)
++#define AC200_EPHY_ADDR(x)		(((x) & 0x1F) << 4)
++#define AC200_EPHY_XMII_SEL		BIT(11)
++#define AC200_EPHY_CALIB(x)		(((x) & 0xF) << 12)
++
++struct ac200_ephy_dev {
++	struct phy_driver	*ephy;
++	struct regmap		*regmap;
++};
++
++static char *ac200_phy_name = "AC200 EPHY";
++
++static void disable_intelligent_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0x1f, 0x0100);	/* switch to page 1 */
++	value = phy_read(phydev, 0x17);
++	value &= ~BIT(3);			/* disable IEEE */
++	phy_write(phydev, 0x17, value);
++	phy_write(phydev, 0x1f, 0x0000);	/* switch to page 0 */
++}
++
++static void disable_802_3az_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, BIT(14) | 0x7);
++	value = phy_read(phydev, 0xe);
++	value &= ~BIT(1);
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, BIT(14) | 0x7);
++	phy_write(phydev, 0xe, value);
++
++	phy_write(phydev, 0x1f, 0x0200);	/* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++}
++
++static int ac200_ephy_config_init(struct phy_device *phydev)
++{
++	const struct ac200_ephy_dev *priv = phydev->drv->driver_data;
++	unsigned int value;
++	int ret;
++
++	phy_write(phydev, 0x1f, 0x0100);	/* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824);	/* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200);	/* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600);	/* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708f);	/* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000);	/* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800);	/* Switch to Page 6 */
++	phy_write(phydev, 0x18, 0x00bc);	/* PHYAFE TRX optimization */
++
++	disable_intelligent_ieee(phydev);	/* Disable Intelligent IEEE */
++	disable_802_3az_ieee(phydev);		/* Disable 802.3az IEEE */
++	phy_write(phydev, 0x1f, 0x0000);	/* Switch to Page 0 */
++
++	value = (phydev->interface == PHY_INTERFACE_MODE_RMII) ?
++		AC200_EPHY_XMII_SEL : 0;
++	ret = regmap_update_bits(priv->regmap, AC200_EPHY_CTL,
++				 AC200_EPHY_XMII_SEL, value);
++	if (ret)
++		return ret;
++
++	/* FIXME: This is probably H6 specific */
++	value = phy_read(phydev, 0x13);
++	value |= BIT(12);
++	phy_write(phydev, 0x13, value);
++
++	return 0;
++}
++
++static const struct mdio_device_id __maybe_unused ac200_ephy_phy_tbl[] = {
++	{ AC200_EPHY_ID, AC200_EPHY_ID_MASK },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(mdio, ac200_ephy_phy_tbl);
++
++static int ac200_ephy_probe(struct platform_device *pdev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(pdev->dev.parent);
++	struct device *dev = &pdev->dev;
++	struct ac200_ephy_dev *priv;
++	struct nvmem_cell *calcell;
++	struct phy_driver *ephy;
++	u16 *caldata, calib;
++	size_t callen;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
++	if (!ephy)
++		return -ENOMEM;
++
++	calcell = devm_nvmem_cell_get(dev, "ephy_calib");
++	if (IS_ERR(calcell)) {
++		dev_err(dev, "Unable to find calibration data!\n");
++		return PTR_ERR(calcell);
++	}
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		dev_err(dev, "Unable to read calibration data!\n");
++		return PTR_ERR(caldata);
++	}
++
++	if (callen != 2) {
++		dev_err(dev, "Calibration data has wrong length: 2 != %lu\n",
++			callen);
++		kfree(caldata);
++		return -EINVAL;
++	}
++
++	calib = *caldata + 3;
++	kfree(caldata);
++
++	ephy->phy_id = AC200_EPHY_ID;
++	ephy->phy_id_mask = AC200_EPHY_ID_MASK;
++	ephy->name = ac200_phy_name;
++	ephy->driver_data = priv;
++	ephy->soft_reset = genphy_soft_reset;
++	ephy->config_init = ac200_ephy_config_init;
++	ephy->suspend = genphy_suspend;
++	ephy->resume = genphy_resume;
++
++	priv->ephy = ephy;
++	priv->regmap = ac200->regmap;
++	platform_set_drvdata(pdev, priv);
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			   AC200_EPHY_RESET_INVALID |
++			   AC200_EPHY_SYSCLK_GATING);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL1,
++			   AC200_EPHY_E_EPHY_MII_IO_EN |
++			   AC200_EPHY_E_LNK_LED_IO_EN |
++			   AC200_EPHY_E_SPD_LED_IO_EN |
++			   AC200_EPHY_E_DPX_LED_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_EPHY_CTL,
++			   AC200_EPHY_LED_POL |
++			   AC200_EPHY_CLK_SEL |
++			   AC200_EPHY_ADDR(1) |
++			   AC200_EPHY_CALIB(calib));
++	if (ret)
++		return ret;
++
++	ret = phy_driver_register(priv->ephy, THIS_MODULE);
++	if (ret) {
++		dev_err(dev, "Unable to register phy\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int ac200_ephy_remove(struct platform_device *pdev)
++{
++	struct ac200_ephy_dev *priv = platform_get_drvdata(pdev);
++
++	phy_driver_unregister(priv->ephy);
++
++	regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++
++	return 0;
++}
++
++static const struct of_device_id ac200_ephy_match[] = {
++	{ .compatible = "x-powers,ac200-ephy" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_ephy_match);
++
++static struct platform_driver ac200_ephy_driver = {
++	.probe		= ac200_ephy_probe,
++	.remove		= ac200_ephy_remove,
++	.driver		= {
++		.name		= "ac200-ephy",
++		.of_match_table	= ac200_ephy_match,
++	},
++};
++module_platform_driver(ac200_ephy_driver);
++
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY driver");
++MODULE_LICENSE("GPL");

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0031-arm64-dts-h6-deinterlace.patch

@@ -0,0 +1,31 @@
+From c009b3b707bbde30fa6ff49ca3075160524ea7b9 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Tue, 26 May 2020 20:08:27 +0200
+Subject: [PATCH 41/44] arm64: dts: h6 deinterlace
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -160,6 +160,18 @@
+ 			};
+ 		};
+
++		deinterlace: deinterlace@1420000 {
++			compatible = "allwinner,sun50i-h6-deinterlace";
++			reg = <0x01420000 0x2000>;
++			clocks = <&ccu CLK_BUS_DEINTERLACE>,
++				 <&ccu CLK_DEINTERLACE>,
++				 <&ccu CLK_MBUS_DEINTERLACE>;
++			clock-names = "bus", "mod", "ram";
++			resets = <&ccu RST_BUS_DEINTERLACE>;
++			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++			iommus = <&iommu 2>;
++		};
++
+ 		video-codec@1c0e000 {
+ 			compatible = "allwinner,sun50i-h6-video-engine";
+ 			reg = <0x01c0e000 0x2000>;

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0043-HACK-h6-Add-HDMI-sound-card.patch

@@ -0,0 +1,53 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 16 Jan 2021 10:58:14 +0100
+Subject: [PATCH] HACK: h6: Add HDMI sound card
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -108,6 +108,24 @@
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
++	sound_hdmi: sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "allwinner-hdmi";
++		simple-audio-card,mclk-fs = <128>;
++		simple-audio-card,frame-inversion;
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++			dai-tdm-slot-num = <2>;
++			dai-tdm-slot-width = <32>;
++		};
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -664,7 +682,6 @@
+ 			dmas = <&dma 4>, <&dma 4>;
+ 			resets = <&ccu RST_BUS_I2S1>;
+ 			dma-names = "rx", "tx";
+-			status = "disabled";
+ 		};
+ 
+ 		spdif: spdif@5093000 {
+@@ -801,6 +818,7 @@
+ 		};
+ 
+ 		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-dw-hdmi";
+ 			reg = <0x06000000 0x10000>;
+ 			reg-io-width = <1>;

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0049-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch

@@ -0,0 +1,110 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:40:20 +0200
+Subject: [PATCH] arm64: dts: allwinner: h6: Add AC200 EPHY related nodes
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 56 ++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -16,6 +16,16 @@
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		clock-frequency = <24000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwm1_pin>;
++		pwms = <&pwm 1 42 0>;
++		status = "disabled";
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -319,6 +329,10 @@
+ 			cpu_speed_grade: cpu-speed-grade@1c {
+ 				reg = <0x1c 0x4>;
+ 			};
++
++			ephy_calib: ephy_calib@2c {
++				reg = <0x2c 0x2>;
++			};
+ 		};
+ 
+ 		timer@3009000 {
+@@ -373,6 +387,13 @@
+ 				drive-strength = <40>;
+ 			};
+ 
++			ext_rmii_pins: rmii_pins {
++				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
++				       "PA5", "PA6", "PA7", "PA8", "PA9";
++				function = "emac";
++				drive-strength = <40>;
++			};
++
+ 			hdmi_pins: hdmi-pins {
+ 				pins = "PH8", "PH9", "PH10";
+ 				function = "hdmi";
+@@ -393,6 +414,11 @@
+ 				function = "i2c2";
+ 			};
+ 
++			i2c3_pins: i2c3-pins {
++				pins = "PB17", "PB18";
++				function = "i2c3";
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+@@ -419,6 +445,11 @@
+ 				bias-pull-up;
+ 			};
+ 
++			pwm1_pin: pwm1-pin {
++				pins = "PB19";
++				function = "pwm1";
++			};
++
+ 			/omit-if-no-ref/
+ 			spi0_pins: spi0-pins {
+ 				pins = "PC0", "PC2", "PC3";
+@@ -652,6 +683,31 @@
+ 			#size-cells = <0>;
+ 		};
+ 
++		i2c3: i2c@5002c00 {
++			compatible = "allwinner,sun6i-a31-i2c";
++			reg = <0x05002c00 0x400>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C3>;
++			resets = <&ccu RST_BUS_I2C3>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_pins>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			ac200: mfd@10 {
++				compatible = "x-powers,ac200";
++				reg = <0x10>;
++				clocks = <&ac200_pwm_clk>;
++
++				ac200_ephy: phy {
++					compatible = "x-powers,ac200-ephy";
++					nvmem-cells = <&ephy_calib>;
++					nvmem-cell-names = "ephy_calib";
++				};
++			};
++		};
++
+ 		emac: ethernet@5020000 {
+ 			compatible = "allwinner,sun50i-h6-emac",
+ 				     "allwinner,sun50i-a64-emac";

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0053-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch

@@ -0,0 +1,60 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Alejandro=20Gonz=C3=A1lez?=
+ <alejandro.gonzalez.correo@gmail.com>
+Date: Sun, 25 Aug 2019 17:05:58 +0200
+Subject: [PATCH] mmc: sunxi: fix unusuable eMMC on some H6 boards by disabling
+ DDR
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Some Allwinner H6 boards have timing problems when dealing with
+DDR-capable eMMC cards. These boards include the Pine H64 and Tanix TX6.
+
+These timing problems result in out of sync communication between the
+driver and the eMMC, which renders the memory unsuable for every
+operation but some basic commmands, like reading the status register.
+
+The cause of these timing problems is not yet well known, but they go
+away by disabling DDR mode operation in the driver. Like on some H5
+boards, it might be that the traces are not precise enough to support
+these speeds. However, Jernej Skrabec compared the BSP driver with this
+driver, and found that the BSP driver configures pinctrl to operate at
+1.8 V when entering DDR mode (although 3.3 V operation is supported), while
+the mainline kernel lacks any mechanism to switch voltages dynamically.
+Finally, other possible cause might be some timing parameter that is
+different on the H6 with respect to other SoCs.
+
+Therefore, as this fix works reliably, the kernel lacks the required
+dynamic pinctrl control for now and a slow eMMC is better than a not
+working eMMC, just disable DDR operation for now on H6-compatible
+devices.
+
+Signed-off-by: Alejandro González <alejandro.gonzalez.correo@gmail.com>
+---
+ drivers/mmc/host/sunxi-mmc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1421,14 +1421,17 @@ static int sunxi_mmc_probe(struct platfo
+ 
+ 	/*
+ 	 * Some H5 devices do not have signal traces precise enough to
+-	 * use HS DDR mode for their eMMC chips.
++	 * use HS DDR mode for their eMMC chips. Other H6 devices operate
++	 * unreliably on HS DDR mode, too.
+ 	 *
+ 	 * We still enable HS DDR modes for all the other controller
+-	 * variants that support them.
++	 * variants that support them properly.
+ 	 */
+ 	if ((host->cfg->clk_delays || host->use_new_timings) &&
+ 	    !of_device_is_compatible(pdev->dev.of_node,
+-				     "allwinner,sun50i-h5-emmc"))
++				     "allwinner,sun50i-h5-emmc") &&
++	    !of_device_is_compatible(pdev->dev.of_node,
++				     "allwinner,sun50i-h6-emmc"))
+ 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
+ 
+ 	ret = mmc_of_parse(mmc);

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0065-wip-fix-H6-4k-60.patch

@@ -0,0 +1,75 @@
+From edc858b1d62ce5ffd8b8d10cc62425af15d48a91 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Wed, 8 Dec 2021 20:42:45 +0100
+Subject: [PATCH] wip: fix H6 4k@60
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 4 ++++
+ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c    | 2 +-
+ 3 files changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index f08d0fded61f..bcd839a3ce80 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -1488,6 +1488,8 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
+ 	/* Override and disable clock termination. */
+ 	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
+ 			      HDMI_3D_TX_PHY_CKCALCTRL);
++	if (mpixelclock == 594000000)
++		dw_hdmi_phy_i2c_write(hdmi, 0x8006, HDMI_3D_TX_PHY_MSM_CTRL);
+ 
+ 	return 0;
+ }
+@@ -2166,6 +2168,8 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi,
+ 	hdmi->hdmi_data.hdcp_enable = 0;
+ 	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
+ 
++	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
++
+ 	/* HDMI Initialization Step B.1 */
+ 	hdmi_av_composer(hdmi, &connector->display_info, mode);
+ 
+@@ -2205,6 +2209,9 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi,
+ 	hdmi_video_sample(hdmi);
+ 	hdmi_tx_hdcp_config(hdmi);
+ 
++	msleep(100);
++	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
++
+ 	dw_hdmi_clear_overflow(hdmi);
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+index 1999db05bc3b..05182418efbb 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+@@ -842,6 +842,10 @@ enum {
+ 	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+ 	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+ 
++/* HDMI_FC_GCP */
++	HDMI_FC_GCP_SET_AVMUTE = 0x2,
++	HDMI_FC_GCP_CLEAR_AVMUTE = 0x1,
++
+ /* FC_DBGFORCE field values */
+ 	HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
+ 	HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+index b64d93da651d..b70bc9de761f 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+@@ -90,7 +90,7 @@ static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = {
+ 		},
+ 	},  {
+ 		594000000, {
+-			{ 0x1a40, 0x0003 },
++			{ 0x1a7c, 0x0003 },
+ 			{ 0x3b4c, 0x0003 },
+ 			{ 0x5a64, 0x0003 },
+ 		},
+-- 
+2.34.1
+

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0066-arm64-dts-allwinner-h6-Fix-Cedrus-IOMMU-again.patch

@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Wed, 12 Oct 2022 23:01:04 +0200
+Subject: [PATCH] arm64: dts: allwinner: h6: Fix Cedrus IOMMU, again
+
+Cedrus actually uses two IOMMU channels. Add the second one.
+
+Fixes: 62a8ccf3a248 ("arm64: dts: allwinner: h6: Fix Cedrus IOMMU usage")
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index e897559d9a89..436cc2a02d1a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -172,7 +172,7 @@ video-codec@1c0e000 {
+ 			resets = <&ccu RST_BUS_VE>;
+ 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ 			allwinner,sram = <&ve_sram 1>;
+-			iommus = <&iommu 3>;
++			iommus = <&iommu 1>, <&iommu 3>;
+ 		};
+ 
+ 		gpu: gpu@1800000 {

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0073-iommu-sun50i-Allow-page-sizes-multiple-of-4096.patch

@@ -0,0 +1,107 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 14 Oct 2022 20:15:43 +0200
+Subject: [PATCH] iommu/sun50i: Allow page sizes multiple of 4096
+
+While peripheral supports only 4K page sizes, we can easily emulate
+support for bigger page sizes, up to 1M. This is done by making multiple
+entries in map function or clearing multiple entries in unmap.
+
+This considerably lowers overhead.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/iommu/sun50i-iommu.c | 44 +++++++++++++++++++++---------------
+ 1 file changed, 26 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
+index d7c5e9b1a087..9944266c4f58 100644
+--- a/drivers/iommu/sun50i-iommu.c
++++ b/drivers/iommu/sun50i-iommu.c
+@@ -593,10 +593,12 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
+ {
+ 	struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
+ 	struct sun50i_iommu *iommu = sun50i_domain->iommu;
+-	u32 pte_index;
++	u32 pte_index, pages, i;
+ 	u32 *page_table, *pte_addr;
+ 	int ret = 0;
+ 
++	pages = size / SPAGE_SIZE;
++
+ 	page_table = sun50i_dte_get_page_table(sun50i_domain, iova, gfp);
+ 	if (IS_ERR(page_table)) {
+ 		ret = PTR_ERR(page_table);
+@@ -604,18 +606,21 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
+ 	}
+ 
+ 	pte_index = sun50i_iova_get_pte_index(iova);
+-	pte_addr = &page_table[pte_index];
+-	if (unlikely(sun50i_pte_is_page_valid(*pte_addr))) {
+-		phys_addr_t page_phys = sun50i_pte_get_page_address(*pte_addr);
+-		dev_err(iommu->dev,
+-			"iova %pad already mapped to %pa cannot remap to %pa prot: %#x\n",
+-			&iova, &page_phys, &paddr, prot);
+-		ret = -EBUSY;
+-		goto out;
++	for (i = 0; i < pages; i++) {
++		pte_addr = &page_table[pte_index + i];
++		if (unlikely(sun50i_pte_is_page_valid(*pte_addr))) {
++			phys_addr_t page_phys = sun50i_pte_get_page_address(*pte_addr);
++			dev_err(iommu->dev,
++				"iova %pad already mapped to %pa cannot remap to %pa prot: %#x\n",
++				&iova, &page_phys, &paddr, prot);
++			ret = -EBUSY;
++			goto out;
++		}
++		*pte_addr = sun50i_mk_pte(paddr, prot);
++		paddr += SPAGE_SIZE;
+ 	}
+ 
+-	*pte_addr = sun50i_mk_pte(paddr, prot);
+-	sun50i_table_flush(sun50i_domain, pte_addr, 1);
++	sun50i_table_flush(sun50i_domain, &page_table[pte_index], pages);
+ 
+ out:
+ 	return ret;
+@@ -626,8 +631,10 @@ static size_t sun50i_iommu_unmap(struct iommu_domain *domain, unsigned long iova
+ {
+ 	struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
+ 	phys_addr_t pt_phys;
++	u32 dte, pages, i;
+ 	u32 *pte_addr;
+-	u32 dte;
++
++	pages = size / SPAGE_SIZE;
+ 
+ 	dte = sun50i_domain->dt[sun50i_iova_get_dte_index(iova)];
+ 	if (!sun50i_dte_is_pt_valid(dte))
+@@ -636,13 +643,14 @@ static size_t sun50i_iommu_unmap(struct iommu_domain *domain, unsigned long iova
+ 	pt_phys = sun50i_dte_get_pt_address(dte);
+ 	pte_addr = (u32 *)phys_to_virt(pt_phys) + sun50i_iova_get_pte_index(iova);
+ 
+-	if (!sun50i_pte_is_page_valid(*pte_addr))
+-		return 0;
++	for (i = 0; i < pages; i++)
++		if (!sun50i_pte_is_page_valid(pte_addr[i]))
++			return 0;
+ 
+-	memset(pte_addr, 0, sizeof(*pte_addr));
+-	sun50i_table_flush(sun50i_domain, pte_addr, 1);
++	memset(pte_addr, 0, sizeof(*pte_addr) * pages);
++	sun50i_table_flush(sun50i_domain, pte_addr, pages);
+ 
+-	return SZ_4K;
++	return size;
+ }
+ 
+ static phys_addr_t sun50i_iommu_iova_to_phys(struct iommu_domain *domain,
+@@ -828,7 +836,7 @@ static int sun50i_iommu_of_xlate(struct device *dev,
+ }
+ 
+ static const struct iommu_ops sun50i_iommu_ops = {
+-	.pgsize_bitmap	= SZ_4K,
++	.pgsize_bitmap	= 0x1ff000,
+ 	.device_group	= sun50i_iommu_device_group,
+ 	.domain_alloc	= sun50i_iommu_domain_alloc,
+ 	.of_xlate	= sun50i_iommu_of_xlate,

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/0077-OrangePi-3-LTS-support.patch

@@ -0,0 +1,393 @@
+From 20d3d43d9daa82d5fa1e937e17b975974572d189 Mon Sep 17 00:00:00 2001
+From: Juliano Dorigão <jdorigao@gmail.com>
+Date: Fri, 3 Mar 2023 16:12:03 -0400
+Subject: [PATCH] OrangePi 3 LTS support
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h6-orangepi-3-lts.dts    | 361 ++++++++++++++++++
+ 2 files changed, 362 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 6a96494a2..ace8159a6 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+new file mode 100644
+index 000000000..67f38b8a1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+@@ -0,0 +1,361 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2023 Jernej Skrabec <jernej.skrabec@gmail.com>
++// Based on sun50i-h6-orangepi-3.dts, which is:
++// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-h6.dtsi"
++#include "sun50i-h6-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "OrangePi 3 LTS";
++	compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	ext_osc32k: ext_osc32k_clk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <32768>;
++		clock-output-names = "ext_osc32k";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "orangepi:red:power";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++
++		led-1 {
++			label = "orangepi:green:status";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the DC jack */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <150000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdca>;
++};
++
++&de {
++	status = "okay";
++};
++
++&dwc3 {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_gmac_3v3>;
++	allwinner,rx-delay-ps = <1500>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_bldo2>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_cldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_cldo1>;
++	vqmmc-supply = <&reg_bldo2>;
++	cap-mmc-hw-reset;
++	non-removable;
++	bus-width = <8>;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_bldo2>;
++	vcc-pd-supply = <&reg_cldo1>;
++	vcc-pg-supply = <&reg_bldo3>;
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&r_rsb {
++	clock-frequency = <100000>;
++	status = "okay";
++
++	axp805: pmic@745 {
++		compatible = "x-powers,axp805", "x-powers,axp806";
++		reg = <0x745>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		x-powers,self-working-mode;
++		vina-supply = <&reg_vcc5v>;
++		vinb-supply = <&reg_vcc5v>;
++		vinc-supply = <&reg_vcc5v>;
++		vind-supply = <&reg_vcc5v>;
++		vine-supply = <&reg_vcc5v>;
++		aldoin-supply = <&reg_vcc5v>;
++		bldoin-supply = <&reg_vcc5v>;
++		cldoin-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-pl-led-ir";
++			};
++
++			reg_aldo2: aldo2 {
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-audio-tv-ephy-mac";
++			};
++
++			/* ALDO3 is shorted to CLDO1 */
++			reg_aldo3: aldo3 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
++			};
++
++			reg_bldo1: bldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18-dram-bias-pll";
++			};
++
++			reg_bldo2: bldo2 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-efuse-pcie-hdmi-pc";
++			};
++
++			reg_bldo3: bldo3 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-pm-pg-dcxoio-wifi";
++			};
++
++			bldo4 {
++				/* unused */
++			};
++
++			reg_cldo1: cldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
++			};
++
++			cldo2 {
++				/* unused */
++			};
++
++			cldo3 {
++				/* unused */
++			};
++
++			reg_dcdca: dcdca {
++				regulator-always-on;
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1160000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdcc: dcdcc {
++				regulator-enable-ramp-delay = <32000>;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1080000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-gpu";
++			};
++
++			reg_dcdcd: dcdcd {
++				regulator-always-on;
++				regulator-min-microvolt = <980000>;
++				regulator-max-microvolt = <980000>;
++				regulator-name = "vdd-sys";
++			};
++
++			reg_dcdce: dcdce {
++				regulator-always-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-name = "vcc-dram";
++			};
++
++			sw {
++				/* unused */
++			};
++		};
++	};
++};
++
++&pwm {
++	status = "okay";
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&rtc {
++	clocks = <&ext_osc32k>;
++};
++
++/delete-node/ &spi0;
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&usb2otg {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usb2phy {
++	usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++	usb0_vbus-supply = <&reg_vcc5v>;
++	usb3_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&usb3phy {
++	status = "okay";
++};
+-- 
+2.39.2
+

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/1004-orange-pi-3-lts-wifi-bt.patch

@@ -0,0 +1,28 @@
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts	2023-07-08 22:25:33.117853247 +0200
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts	2023-07-08 22:26:25.418940556 +0200
+@@ -103,6 +103,25 @@
+ 		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
+ 		post-power-on-delay-ms = <200>;
+ 	};
++
++	sunxi-info {
++		compatible = "allwinner,sun50i-h6-sys-info";
++		status = "okay";
++	};
++
++	addr_mgt: addr-mgt {
++		compatible = "allwinner,sunxi-addr_mgt";
++		type_addr_wifi = <0x2>;
++		type_addr_bt = <0x2>;
++		type_addr_eth = <0x2>;
++		status = "okay";
++	};
++
++	dump_reg: dump_reg@20000 {
++		compatible = "allwinner,sunxi-dump-reg";
++		reg = <0x0 0x03001000 0x0 0x0f20>;
++		status = "okay";
++	};
+ };
+ 
+ &cpu0 {

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/2000-arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch

@@ -0,0 +1,67 @@
+From ba3b30a80ac2c388d48c58fbee242466d51fbfd8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Dec 2020 11:15:34 -0600
+Subject: [PATCH 177/389] arm64: dts: allwinner: Enforce consistent MMC
+ numbering
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 77b5349f6087..9e0e17179839 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -18,6 +18,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	chosen {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index a56fae761a1f..2159fa336d75 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -6,6 +6,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index ca1d287a0a01..3feac99556f3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -17,6 +17,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-- 
+2.35.3
+

recipes-kernel/linux/linux-mainline-6.1.9/orange-pi-3lts/orangepi-3lts.cfg

@@ -0,0 +1,4 @@
+CONFIG_SPARD_WLAN_SUPPORT=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_INIT_STACK_NONE=y
+CONFIG_PHY_SUN50I_USB3=y