This is used for video output using video bridge implementation of
MIPI-DSI, like with the recently added dw_mipi_dsi_rockchip.c
driver.
The original code path when the UCLASS_DISPLAY device is found is
untouched. The video bridge branch is taken only when the
UCLASS_VIDEO_BRIDGE device is found at the remote endpoint's parent.
This was tested to work on Pinephone Pro.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Chris Morgan <macromorgan@hotmail.com>
This just needs some extra clocks enabled, and different registers
configured. Copied from Linux, just like the original submitter
of this driver did for rk3568.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
The driver is for panels based on the Himax HX8394 controller, such as the
HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface.
This panel is used in Pinephone Pro.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Cc: Anatolij Gustschin <agust@denx.de>
cpll in U-Boot runs at 384 MHz, set various VOP related clocks to produce
roughly 400 and 100 MHz just like in Linux.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
The limit needs to be raised as soon as possible to prevent boot loops
on empty or removed battery. The default 450mA limit is crossed when
eMMC or SD card starts seeing reads in SPL after DRAM was already
enabled in TPL.
Running this PMIC setup in main U-Boot binary is a bit too late, and
1.5A is a bit too low for a completely battery-less boot. That would
need the input current limit to be raised before initializing DRAM
in TPL and at least to 2A, because peak power consumption in Linux
during boot is currently 8W.
But this fix is good enough to prevent boot loops when the phone can still
get ~100mA from the battery to cover the difference between 450 mA current
limit and ~550 mA needed to load main U-Boot from eMMC while the DRAM
is already initialized by TPL.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
This fixes access to camera sensor over I2C during probe time in
the kernel. (Kernel will fix I/0 port voltage by itself, but the
timing depends on probe order of the drivers, so the fix can
come after the camera sensor driver already failed to probe.)
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Failure can happen when i2c is used without initializing pinctrl properly,
which U-Boot happily allows in SPL. Without this fix, further I2C access would
fail, even after proper pinctrl initialization.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Some callers expect to call this with NULL font name to select the
default font (eg. boot/scene.c). Without handling the NULL condition
U-Boot crashes instead of displaying a bootflow GUI menu.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Use proper register base and access method to access GRF registers.
GRF registers start at a completely different base, and need special
access method, that sets the change mask in the 16 MSBs.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
If phy is not defined in DT (eg. on rk3399), generic_phy_get_by_name
will return -ENODATA. Handle that case correctly.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
pllref_clk is unused after being retrieved. fin needs to be set
to dsi->ref clock's rate for the following calculation to work.
Otherwise fin is undefined, and calculation return bogus number
based on undefined variable.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
&priv->phy is always true. Compiler warns about this loudly.
Use a propper check for phy device allocation. Without this fix
using this driver with SoC that doesn't use external phy (eg. RK3399)
doesn't work.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
These must be read from timings->flags, like other DSI HOST drivers do.
And they must not be inverted either. Low means low.
Without this fix, panel drivers that set *SYNC_LOW produce corrupted
output on screen (shifted horizobnntally and vertivally by back porch
distance).
Signed-off-by: Ondrej Jirman <megi@xff.cz>
rk3588 driver:
- Sync the reset driver with kernel code;
- Enable pcie controller and phy support;
- Enable USB controller and phy support;
Board level dts and config update:
- boost eMMC performance for some of rk3399 boards;
- boot from SPI NOR flash for rk356x boards;
- Other board level updates;
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.
Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1492992 bytes read in 129 ms (11 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x16c800
1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s
The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
The phycore-rk3288 SPL binary is reaching the limits of 32KB very often.
Enable CONFIG_LTO to reduce the size of the SPL and make the board more
future proof for changes increasing the SPL size.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
If u-boot is installed on the internal emmc, then this will
allow to boot without failure.
Signed-off-by: Wolfgang Zarre <lxdev12@zirdeon.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable pinctrl for sdhci in SPL to support loading of FIT image from SD
and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3588-rock-5b with new defaults.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3588-evb with new defaults.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config options to include useful gpio and regulator cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Remove CONFIG_DEBUG_UART_ANNOUNCE=y to remove debug messages.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful
across RK3588 platform. Select them from arch Kconfig.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.
Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1384448 bytes read in 119 ms (11.1 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x152000
1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3568-rock-3a with new defaults.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Remove the CONFIG_SPL_PMIC_RK8XX=y option, the pmic is not used in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3568-evb with new defaults.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config options to include useful gpio, i2c, pmic and regulator cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Add config options to enable support for the RK809 PMIC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add bootph-all prop to xin24m clock node, it is referenced by cru node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use the same prop as linux to control the use of fifo or dma mode. Also
add a u-boot,spl-sfc-no-dma prop to control the same in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.
Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
[eugen.hristev@collabora.com: minor tweaks]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: add PCIe pins]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: adapt to kernel node]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin.
Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected
offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage
output fit before the 0x60000 offset in u-boot-rockchip-spi.bin.
=> sf probe
SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1442304 bytes read in 27 ms (50.9 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x160200
1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4.
Also add missing flags to indicate the supported MMC modes.
Using mmc read command to read 32 MiB data shows following improvement:
=> time mmc read 10000000 2000 10000
Before: time: 3.178 seconds
After: time: 0.402 seconds
This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
