This is without the SD controller support, because I have a broken
uSD slot on my board. Until that's fixed, it needs to be disabled.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
There's no other way to load bitstream file to Zynq 7000 via SPL
otherwise, and SPL just reports:
zynq_validate_bitstream: Bitstream is not validated yet (diff 6c)
spl_fit_upload_fpga: Cannot load the image to the FPGA
This is similar to code in boot/image-board.c
Signed-off-by: Ondrej Jirman <megi@xff.cz>
cpll in U-Boot runs at 384 MHz, set various VOP related clocks to produce
roughly 400 and 100 MHz just like in Linux.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
This is used for video output using video bridge implementation of
MIPI-DSI, like with the recently added dw_mipi_dsi_rockchip.c
driver.
The original code path when the UCLASS_DISPLAY device is found is
untouched. The video bridge branch is taken only when the
UCLASS_VIDEO_BRIDGE device is found at the remote endpoint's parent.
This was tested to work on Pinephone Pro.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Chris Morgan <macromorgan@hotmail.com>
Calculate burst mode overhead in one place for both internal
and external PHY use case and exit if out of range, instead
of ignoring the wrong value.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Shows a menu of items that can be controlled using touch panel.
This is useful for touch based devices like tablets to select
alternative boot options (multi-boot).
Signed-off-by: Ondrej Jirman <megous@megous.com>
Touchapnel devices are useful in u-boot for implementation of boot
menu user interfaces on tablets and other touch based devices.
This uclass implements start, stop and get_touches interface methods.
Signed-off-by: Ondrej Jirman <megous@megous.com>
The commit 3b804b370d ("mmc: rockchip_sdhci: Disable DMA mode using a
device tree property") and commit 2cc6cde647 ("mmc: rockchip_sdhci:
Limit number of blocks read in a single command") implemented a
workaround to fix loading a part of TF-A into SRAM from eMMC in SPL.
This has resulted in very slow read performance of FIT from eMMC in SPL
on RK3588.
Change to make use of a bounce buffer to significantly improve the read
performance when malloc_limit is large enough and use PIO mode as fall
back.
Also update the size of align_buffer to use SDHCI_DEFAULT_BOUNDARY_SIZE
instead of a hardcoded 512 * 1024.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://patchwork.ozlabs.org/patch/1895377/
UART pinctrl for serial is typically applied multiple times:
- in external TPL
- in SPL for DEBUG_UART in board_debug_uart_init()
- in SPL using pinctrl from DT
- in pre-reloc phase using pinctrl from DT
- after relocation using pinctrl from DT
Skip including UART pinctrl for the the pre-reloc phase to save time
during boot. On a Radxa ROCK 5B this reduce boot time by ~150 ms.
After this a warning may be shown with LOGLEVEL=5 (or higher), it is
safe to ignore this warning as device probe is successful even when
pinctrl cannot be applied:
ns16550_serial serial@feb50000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
UART pinctrl for serial is typically applied multiple times:
- in external TPL
- in SPL for DEBUG_UART in board_debug_uart_init()
- in SPL using pinctrl from DT
- in pre-reloc phase using pinctrl from DT
- after relocation using pinctrl from DT
Skip including UART pinctrl for the the pre-reloc phase to save time
during boot. On a Radxa ZERO 3W this reduce boot time by ~120 ms.
After this a warning may be shown with LOGLEVEL=5 (or higher), it is
safe to ignore this warning as device probe is successful even when
pinctrl cannot be applied:
ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
UART pinctrl for serial is typically applied multiple times:
- in external TPL
- in SPL using pinctrl from DT
- in pre-reloc phase using pinctrl from DT
- after relocation using pinctrl from DT
Skip including UART pinctrl for the the pre-reloc phase to save time
during boot. On a Radxa ROCK Pi S this reduce boot time by ~80 ms.
After this a warning may be shown with LOGLEVEL=5 (or higher), it is
safe to ignore this warning as device probe is successful even when
pinctrl cannot be applied:
ns16550_serial serial@ff0a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Initializing a clock driver to read a known static clock rate can take
some time at U-Boot proper pre-reloc phase.
Change to first try and read clock rate from DT to speed up boot time,
fall back to getting the clock rate from clock driver.
This help reduce boot time by around:
- ~35ms on a Radxa ROCK Pi 4 (RK3399)
- ~15ms on a Radxa ZERO 3W (RK3566)
Time that is wasted getting a static rate known at compile time.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add aliases for gpio controllers to soc u-boot dtsi files that are
missing aliases in soc dtsi files to ensure dev_seq() return the
expected number when a gpio controller is included in SPL.
Also drop the aliases from rk3288-u-boot.dtsi, they are already part of
rk3288.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add a request() ops that call pinctrl_gpio_request() when the required
gpio-ranges prop has been defined to signal pinctrl driver to use gpio
pinmux.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Use the pinctrl pin offset to get_gpio_mux() to remove the bank num
dependency and instead only use the bank num to assign a bank name.
Most Rockchip SoCs use all 32 pins of each gpio controller, meaning the
pinctrl pin offset typically is aligned to 32.
However, for gpio0 on RK3288 only 24 pins are used meaning the pinctrl
pin offset start at pin 24 for gpio1. Use DIV_ROUND_UP to get the 32 pin
aligned bank num.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Get pinctrl device from gpio-ranges phandle when the property exists,
fallback to get the first pinctrl device.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Implement gpio_request_enable() ops so that the gpio request() ops can
be implemented and a gpio requested pin automatically is pinmuxed for
gpio use, similar to Linux kernel.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add get_pins_count(), get_pin_name() and get_pin_muxing() ops to support
the pinmux status cmd.
=> pinmux dev pinctrl
dev: pinctrl
=> pinmux status
GPIO0_A0 : gpio
GPIO0_A1 : func-1
GPIO0_A2 : gpio
GPIO0_A3 : gpio
GPIO0_A4 : func-1
GPIO0_A5 : gpio
GPIO0_A6 : gpio
GPIO0_A7 : func-1
GPIO0_B0 : gpio
GPIO0_B1 : func-1
GPIO0_B2 : func-1
GPIO0_B3 : gpio
[...]
The change to use ENOENT for unrouted pins also help hide a "Error -22"
message for unrouted pins using the gpio status -a cmd.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a way to get_gpio_mux() based on the pinctrl pin offset, use -1 as
banknum to use the pinctrl pin offset mode instead of bank pin offset.
This mode will be used by the gpio driver to ensure a pin used by gpio
request() and get_function() ops always refer to the same pinctrl pin.
Also add verify_config() of banknum and index to avoid an out of range
access of the pin_banks array, i.e. with gpio6 on rk3066a.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a pin_to_bank() helper that can locate a pin bank based on the pin
offset, to be used in get_gpio_mux() and gpio_request_enable() ops.
Reset ctrl->nr_pins to 0 so that pin_to_bank() can locate a bank after
the second probe in U-Boot proper.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
The alignment hole caused by cmdidx in struct mmc_cmd cause strange
issues together with the peephole2 optimization on Amlogic SoCs.
Following was observed while working on SPL support for Amlogic SoCs.
sd_get_capabilities() normally issue a CMD55 followed by a CMD51.
However, on at least Amlogic S905 (Cortex-A53) and S905X3 (Cortex-A55),
CMD55 was instead followed by CMD8 (and a few reties) in SPL.
Code from the call site:
cmd.cmdidx = SD_CMD_APP_SEND_SCR; // 51
...
data.blocksize = 8;
...
err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
Running the code with MMC_TRACE enabled shows:
CMD_SEND:55
ARG 0x50480000
MMC_RSP_R1,5,6,7 0x00000920
CMD_SEND:8
ARG 0x00000000
RET -110
Removing the alignment hole by changing cmdidx from ushort to uint or
building with -fno-peephole2 flag seem to resolve this issue.
CMD_SEND:55
ARG 0x50480000
MMC_RSP_R1,5,6,7 0x00000920
CMD_SEND:51
ARG 0x00000000
MMC_RSP_R1,5,6,7 0x00000920
Same issue was observed building U-Boot with gcc 8 - 13.
Remove this alignment hole by changing cmdidx from ushort to uint.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Remove the rockchip,rk3399-dwc3 compatible from the dwc3-of-simple
driver now that all boards have changed to use the dwc3-generic driver.
Also remove the amlogic,meson-gxl-dwc3 compatible, it is no longer in
use by any device tree in mainline linux or U-Boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
dev_get_driver_ops() may return NULL when the udevice is invalid.
Move the ops check to top of functions to consistently return -ENOSYS
when ops is unimplemented and prevent trying to access uclass plat data,
also add missing NULL checks to suspend ops.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
(cherry picked from commit 4386ab9118)
On some boards a PMIC regulator is flagged with regulator-on-in-suspend
and does not define any suspend or max microvolt, e.g. on Radxa ROCK 3A:
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
This result in suspend_uV having the value -ENODATA after probe.
This negative voltage, -ENODATA, gets missinterpreted and result in an
unexpected voltage being set by autoset.
E.g. on Radxa ROCK 3A the vcc_ddr regulator by default have a normal and
suspend voltage value of 0.5v. However, due to this missinterpretation
the suspend voltage end up beind set to 0.5625v instead.
Fix this by skip calling regulator_set_suspend_value() in autoset and
also protect calling set value ops when input value is -ENODATA.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
(cherry picked from commit f417c14d88)
