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clk: rockchip: Add clocks used by VOP and mipi-dsi on rk3399

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These need to be handled for VOP/MIPI-DSI support.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
This commit is contained in:
Ondrej Jirman
2023-05-22 00:19:02 +02:00
parent bdb40f1567
commit 0087761618
1 changed files with 21 additions and 0 deletions
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21
drivers/clk/rockchip/clk_rk3399.c
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@@ -1001,6 +1001,8 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case PCLK_WDT:
rate = rk3399_alive_get_clk(priv->cru);
break;
case SCLK_DPHY_PLL:
return 24000000;
default:
log_debug("Unknown clock %lu\n", clk->id);
return -ENOENT;
@@ -1064,6 +1066,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case DCLK_VOP1:
ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
break;
case ACLK_VOP0:
case HCLK_VOP0:
case ACLK_VOP1:
case HCLK_VOP1:
case HCLK_SD:
@@ -1168,6 +1172,11 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
return rk3399_gmac_set_parent(clk, parent);
case SCLK_PCIEPHY_REF:
return rk3399_pciephy_set_parent(clk, parent);
case DCLK_VOP1_DIV:
case DCLK_VOP0_DIV:
case DCLK_VOP1:
case DCLK_VOP0:
return 0;
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1261,6 +1270,12 @@ static int rk3399_clk_enable(struct clk *clk)
if (readl(&priv->cru->clksel_con[18]) & BIT(10))
rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
break;
case SCLK_DPHY_TX0_CFG:
rk_clrreg(&priv->cru->clkgate_con[21], BIT(1));
break;
case PCLK_VIO_GRF:
rk_clrreg(&priv->cru->clkgate_con[29], BIT(12));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;
@@ -1356,6 +1371,12 @@ static int rk3399_clk_disable(struct clk *clk)
if (readl(&priv->cru->clksel_con[18]) & BIT(10))
rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
break;
case SCLK_DPHY_TX0_CFG:
rk_setreg(&priv->cru->clkgate_con[21], BIT(1));
break;
case PCLK_VIO_GRF:
rk_setreg(&priv->cru->clkgate_con[29], BIT(12));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;