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Fix unreliable detection of DRAM size on Orange Pi 3

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In mctl_mem_matches() we need to flush/invalidate cache, so that
we can be sure, we're actually reading back data from DRAM, and
not values cached in data cache.

This fixes unreliable detection of DRAM size on Orange Pi 3.

Signed-off-by: Ondrej Jirman <megous@megous.com>
This commit is contained in:
Ondrej Jirman
2019-07-17 02:28:23 +02:00
parent cb9c7bcb92
commit c2675f18c0
1 changed files with 3 additions and 1 deletions
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4
arch/arm/mach-sunxi/dram_helpers.c
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@@ -31,7 +31,9 @@ bool mctl_mem_matches(u32 offset)
/* Try to write different values to RAM at two addresses */
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
dsb();
/* Make sure values are written and that we don't get a cached
* value back. */
flush_dcache_all();
/* Check if the same value is actually observed when reading back */
return readl(CONFIG_SYS_SDRAM_BASE) ==
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);