From c2675f18c0dc3f1892d96a0d7d608ed74d3fc636 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 17 Jul 2019 02:28:23 +0200 Subject: [PATCH] Fix unreliable detection of DRAM size on Orange Pi 3 In mctl_mem_matches() we need to flush/invalidate cache, so that we can be sure, we're actually reading back data from DRAM, and not values cached in data cache. This fixes unreliable detection of DRAM size on Orange Pi 3. Signed-off-by: Ondrej Jirman --- arch/arm/mach-sunxi/dram_helpers.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 239ab421a8b..470d26bd9c9 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -31,7 +31,9 @@ bool mctl_mem_matches(u32 offset) /* Try to write different values to RAM at two addresses */ writel(0, CONFIG_SYS_SDRAM_BASE); writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); - dsb(); + /* Make sure values are written and that we don't get a cached + * value back. */ + flush_dcache_all(); /* Check if the same value is actually observed when reading back */ return readl(CONFIG_SYS_SDRAM_BASE) == readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);