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sunxi: Rename pll10 to pll_de to avoid confusion

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A83T SoC has PLL_DE at pll9. Change the name to make it less
confusing when we'll add DE2 support for A83T.

Signed-off-by: Ondrej Jirman <megous@megous.com>
This commit is contained in:
Ondrej Jirman
2018-07-09 15:28:13 +02:00
parent f67392426f
commit 71ded8dc01
3 changed files with 3 additions and 3 deletions
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2
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@@ -523,7 +523,7 @@ void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);
void clock_set_pll3_factors(int m, int n);
void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
void clock_set_pll10(unsigned int hz);
void clock_set_pll_de(unsigned int hz);
void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
void clock_set_mipi_pll(unsigned int hz);
unsigned int clock_get_pll3(void);

2
arch/arm/mach-sunxi/clock_sun6i.c
View File

@@ -256,7 +256,7 @@ done:
#endif
#ifdef CONFIG_SUNXI_DE2
void clock_set_pll10(unsigned int clk)
void clock_set_pll_de(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

2
drivers/video/sunxi/sunxi_de2.c
View File

@@ -44,7 +44,7 @@ static void sunxi_de2_composer_init(void)
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
#endif
clock_set_pll10(432000000);
clock_set_pll_de(432000000);
/* Set DE parent to pll10 */
clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,