From 71ded8dc01bf817e3fbd56afddf64b47eba4f34c Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 9 Jul 2018 15:28:13 +0200 Subject: [PATCH] sunxi: Rename pll10 to pll_de to avoid confusion A83T SoC has PLL_DE at pll9. Change the name to make it less confusing when we'll add DE2 support for A83T. Signed-off-by: Ondrej Jirman --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +- arch/arm/mach-sunxi/clock_sun6i.c | 2 +- drivers/video/sunxi/sunxi_de2.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 296f9d11bc2..2ff825a359a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -523,7 +523,7 @@ void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); void clock_set_pll3_factors(int m, int n); void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); -void clock_set_pll10(unsigned int hz); +void clock_set_pll_de(unsigned int hz); void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); void clock_set_mipi_pll(unsigned int hz); unsigned int clock_get_pll3(void); diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 427b296946d..b889c72d3ef 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -256,7 +256,7 @@ done: #endif #ifdef CONFIG_SUNXI_DE2 -void clock_set_pll10(unsigned int clk) +void clock_set_pll_de(unsigned int clk) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 8333ddc44c0..c82394b3874 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -44,7 +44,7 @@ static void sunxi_de2_composer_init(void) writel(reg_value, SUNXI_SRAMC_BASE + 0x04); #endif - clock_set_pll10(432000000); + clock_set_pll_de(432000000); /* Set DE parent to pll10 */ clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,