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add a kSlowSSSE3 feature for CPUInfo
This is meant to be used for run-time detection of slow platforms regarding instructions like pshufb and bsr. Adapted from libvpx patch: https://chromium-review.googlesource.com/#/c/367731 Change-Id: I2c22fbb9aae699d87a041393ba1ad5f1f21ff640
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@ -95,26 +95,62 @@ static WEBP_INLINE uint64_t xgetbv(void) {
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#endif
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#if defined(__i386__) || defined(__x86_64__) || defined(WEBP_MSC_SSE2)
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// helper function for run-time detection of slow SSSE3 platforms
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static int CheckSlowModel(int info) {
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// Table listing display models with longer latencies for the bsr instruction
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// (ie 2 cycles vs 10/16 cycles) and some SSSE3 instructions like pshufb.
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// Refer to Intel 64 and IA-32 Architectures Optimization Reference Manual.
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static const uint8_t kSlowModels[] = {
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0x37, 0x4a, 0x4d, // Silvermont Microarchitecture
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0x1c, 0x26, 0x27 // Atom Microarchitecture
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};
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const uint32_t model = ((info & 0xf0000) >> 12) | ((info >> 4) & 0xf);
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const uint32_t family = (info >> 8) & 0xf;
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if (family == 0x06) {
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size_t i;
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for (i = 0; i < sizeof(kSlowModels) / sizeof(kSlowModels[0]); ++i) {
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if (model == kSlowModels[i]) return 1;
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}
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}
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return 0;
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}
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static int x86CPUInfo(CPUFeature feature) {
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int max_cpuid_value;
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int cpu_info[4];
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int is_intel = 0;
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// get the highest feature value cpuid supports
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GetCPUInfo(cpu_info, 0);
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max_cpuid_value = cpu_info[0];
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if (max_cpuid_value < 1) {
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return 0;
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} else {
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const int VENDOR_ID_INTEL_EBX = 0x756e6547; // uneG
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const int VENDOR_ID_INTEL_EDX = 0x49656e69; // Ieni
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const int VENDOR_ID_INTEL_ECX = 0x6c65746e; // letn
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is_intel = (cpu_info[1] == VENDOR_ID_INTEL_EBX &&
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cpu_info[2] == VENDOR_ID_INTEL_ECX &&
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cpu_info[3] == VENDOR_ID_INTEL_EDX); // genuine Intel?
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}
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GetCPUInfo(cpu_info, 1);
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if (feature == kSSE2) {
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return 0 != (cpu_info[3] & 0x04000000);
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return !!(cpu_info[3] & (1 << 26));
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}
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if (feature == kSSE3) {
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return 0 != (cpu_info[2] & 0x00000001);
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return !!(cpu_info[2] & (1 << 0));
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}
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if (feature == kSlowSSSE3) {
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if (is_intel && (cpu_info[2] & (1 << 0))) { // SSSE3?
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return CheckSlowModel(cpu_info[0]);
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}
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return 0;
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}
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if (feature == kSSE4_1) {
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return 0 != (cpu_info[2] & 0x00080000);
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return !!(cpu_info[2] & (1 << 19));
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}
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if (feature == kAVX) {
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// bits 27 (OSXSAVE) & 28 (256-bit AVX)
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@ -126,7 +162,7 @@ static int x86CPUInfo(CPUFeature feature) {
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if (feature == kAVX2) {
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if (x86CPUInfo(kAVX) && max_cpuid_value >= 7) {
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GetCPUInfo(cpu_info, 7);
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return ((cpu_info[1] & 0x00000020) == 0x00000020);
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return !!(cpu_info[1] & (1 << 5));
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}
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}
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return 0;
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@ -184,4 +220,3 @@ VP8CPUInfo VP8GetCPUInfo = mipsCPUInfo;
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#else
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VP8CPUInfo VP8GetCPUInfo = NULL;
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#endif
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@ -132,6 +132,7 @@ extern "C" {
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typedef enum {
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kSSE2,
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kSSE3,
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kSlowSSSE3, // special feature for slow SSSE3 architectures
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kSSE4_1,
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kAVX,
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kAVX2,
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