dany/facetimehd
1
0
Fork 0
mirror of https://github.com/patjak/facetimehd.git synced 2026-04-09 19:10:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

Updated S2 PLLs (markdown)

Patrik Jakobsson
2015-09-05 15:14:34 +02:00
parent 4629d6fc94
commit f96f6e0ba7
1 changed files with 6 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
S2-PLLs.md

@@ -7,7 +7,8 @@ PLL reference clock. Can be set to 24 or 25 MHz.
* Bit 3: 0 = 24MHz, 1 = 25MHz
### 0:0x14
TODO
Register is written with value 0x3 after sleeping for 10ms on a soft s2 PLL reset.
* Written with values: 0x3
### 0:0x20
PLL settings for 24MHz refclock
@@ -30,10 +31,12 @@ Used during PLL reset
* Written to values: 0x0, 0x40
### 0:0x9c
TODO
Used for DDR PHY soft reset sequence.
* Written to values: 0xfffff
### 0:0x100
TODO
Used during PLL reset
* Written to values: 0xbcbc1500
### 0:0x510
PLL settings for 25MHz