diff --git a/S2-PLLs.md b/S2-PLLs.md
index 980bf80..af6a7dd 100644
--- a/S2-PLLs.md
+++ b/S2-PLLs.md
@@ -7,7 +7,8 @@ PLL reference clock. Can be set to 24 or 25 MHz.
 * Bit 3: 0 = 24MHz, 1 = 25MHz
 
 ### 0:0x14
-TODO
+Register is written with value 0x3 after sleeping for 10ms on a soft s2 PLL reset.
+* Written with values: 0x3
 
 ### 0:0x20
 PLL settings for 24MHz refclock
@@ -30,10 +31,12 @@ Used during PLL reset
 * Written to values: 0x0, 0x40
 
 ### 0:0x9c
-TODO
+Used for DDR PHY soft reset sequence.
+* Written to values: 0xfffff
 
 ### 0:0x100
-TODO
+Used during PLL reset
+* Written to values: 0xbcbc1500
 
 ### 0:0x510
 PLL settings for 25MHz