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a867392791
This converts 1 usage of this option to the non-SPL form, since there is no SPL_MIPS_CM defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
142 lines
3.7 KiB
C
142 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* MIPS Coherence Manager (CM) Register Definitions
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*
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* Copyright (c) 2016 Imagination Technologies Ltd.
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*/
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#ifndef __MIPS_ASM_CM_H__
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#define __MIPS_ASM_CM_H__
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/* Global Control Register (GCR) offsets */
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#define GCR_CONFIG 0x0000
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#define GCR_BASE 0x0008
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#define GCR_BASE_UPPER 0x000c
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#define GCR_CONTROL 0x0010
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#define GCR_ACCESS 0x0020
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#define GCR_REV 0x0030
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#define GCR_GIC_BASE 0x0080
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#define GCR_CPC_BASE 0x0088
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#define GCR_REG0_BASE 0x0090
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#define GCR_REG0_MASK 0x0098
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#define GCR_REG1_BASE 0x00a0
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#define GCR_REG1_MASK 0x00a8
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#define GCR_REG2_BASE 0x00b0
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#define GCR_REG2_MASK 0x00b8
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#define GCR_REG3_BASE 0x00c0
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#define GCR_REG3_MASK 0x00c8
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#define GCR_CPC_STATUS 0x00f0
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#define GCR_L2_CONFIG 0x0130
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#define GCR_L2_TAG_ADDR 0x0600
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#define GCR_L2_TAG_ADDR_UPPER 0x0604
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#define GCR_L2_TAG_STATE 0x0608
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#define GCR_L2_TAG_STATE_UPPER 0x060c
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#define GCR_L2_DATA 0x0610
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#define GCR_L2_DATA_UPPER 0x0614
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#define GCR_Cx_COHERENCE 0x2008
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#define GCR_Cx_OTHER 0x2018
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#define GCR_Cx_ID 0x2028
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#define GCR_CO_COHERENCE 0x4008
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/* GCR_CONFIG fields */
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#define GCR_CONFIG_NUM_CLUSTERS_SHIFT 23
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#define GCR_CONFIG_NUM_CLUSTERS (0x7f << 23)
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#define GCR_CONFIG_NUMIOCU_SHIFT 8
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#define GCR_CONFIG_NUMIOCU (0xff << 8)
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#define GCR_CONFIG_PCORES_SHIFT 0
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#define GCR_CONFIG_PCORES (0xff << 0)
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/* GCR_BASE fields */
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#define GCR_BASE_SHIFT 15
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#define CCA_DEFAULT_OVR_SHIFT 5
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#define CCA_DEFAULT_OVR_MASK (0x7 << 5)
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#define CCA_DEFAULT_OVREN (0x1 << 4)
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#define CM_DEFAULT_TARGET_SHIFT 0
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#define CM_DEFAULT_TARGET_MASK (0x3 << 0)
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/* GCR_CONTROL fields */
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#define GCR_CONTROL_SYNCCTL (0x1 << 16)
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/* GCR_REV CM versions */
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#define GCR_REV_CM3 0x0800
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/* GCR_GIC_BASE fields */
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#define GCR_GIC_BASE_ADDRMASK_SHIFT 7
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#define GCR_GIC_BASE_ADDRMASK (0x1ffffff << 7)
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#define GCR_GIC_EN (0x1 << 0)
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/* GCR_CPC_BASE fields */
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#define GCR_CPC_BASE_ADDRMASK_SHIFT 15
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#define GCR_CPC_BASE_ADDRMASK (0x1ffff << 15)
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#define GCR_CPC_EN (0x1 << 0)
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/* GCR_REGn_MASK fields */
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#define GCR_REGn_MASK_ADDRMASK_SHIFT 16
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#define GCR_REGn_MASK_ADDRMASK (0xffff << 16)
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#define GCR_REGn_MASK_CCAOVR_SHIFT 5
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#define GCR_REGn_MASK_CCAOVR (0x7 << 5)
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#define GCR_REGn_MASK_CCAOVREN (1 << 4)
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#define GCR_REGn_MASK_DROPL2 (1 << 2)
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#define GCR_REGn_MASK_CMTGT_SHIFT 0
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#define GCR_REGn_MASK_CMTGT (0x3 << 0)
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#define GCR_REGn_MASK_CMTGT_DISABLED 0x0
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#define GCR_REGn_MASK_CMTGT_MEM 0x1
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#define GCR_REGn_MASK_CMTGT_IOCU0 0x2
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#define GCR_REGn_MASK_CMTGT_IOCU1 0x3
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/* GCR_CPC_STATUS fields */
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#define GCR_CPC_EX (0x1 << 0)
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/* GCR_L2_CONFIG fields */
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#define GCR_L2_CONFIG_ASSOC_SHIFT 0
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#define GCR_L2_CONFIG_ASSOC_BITS 8
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#define GCR_L2_CONFIG_LINESZ_SHIFT 8
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#define GCR_L2_CONFIG_LINESZ_BITS 4
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#define GCR_L2_CONFIG_SETSZ_SHIFT 12
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#define GCR_L2_CONFIG_SETSZ_BITS 4
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#define GCR_L2_CONFIG_BYPASS (1 << 20)
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/* GCR_Cx_COHERENCE */
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#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0)
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#define GCR_Cx_COHERENCE_EN (0x1 << 0)
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/* GCR_Cx_OTHER fields */
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#define GCR_Cx_OTHER_CORENUM_SHIFT 16
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#define GCR_Cx_OTHER_CORENUM (0xffff << 16)
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#ifndef __ASSEMBLY__
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#include <asm/io.h>
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#include <linux/bitops.h>
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#if IS_ENABLED(CONFIG_MIPS_CM)
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static inline void *mips_cm_base(void)
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{
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return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
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}
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static inline unsigned long mips_cm_l2_line_size(void)
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{
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unsigned long l2conf, line_sz;
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l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG);
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line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT;
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line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
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return line_sz ? (2 << line_sz) : 0;
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}
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#else
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static inline void *mips_cm_base(void)
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{
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return NULL;
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}
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static inline unsigned long mips_cm_l2_line_size(void)
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{
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return 0;
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}
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif /* __MIPS_ASM_CM_H__ */
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