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464b96bb80
This path add a new helper allowing to prefetch and lock instructions into cache. This is useful very early in the boot when no RAM is available yet. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
115 lines
2.8 KiB
C
115 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Cache operations for the cache instruction.
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*
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* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
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* (C) Copyright 1999 Silicon Graphics, Inc.
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*/
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#ifndef __ASM_CACHEOPS_H
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#define __ASM_CACHEOPS_H
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#ifndef __ASSEMBLY__
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static inline void mips_cache(int op, const volatile void *addr)
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{
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#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
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__builtin_mips_cache(op, addr);
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#else
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__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
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#endif
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}
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#define MIPS32_WHICH_ICACHE 0x0
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#define MIPS32_FETCH_AND_LOCK 0x7
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#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
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/* Prefetch and lock instructions into cache */
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static inline void icache_lock(void *func, size_t len)
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{
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int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
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for (i = 0; i < lines; i++) {
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asm volatile (" cache %0, %1(%2)"
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: /* No Output */
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: "I" ICACHE_LOAD_LOCK,
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"n" (i * ARCH_DMA_MINALIGN),
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"r" (func)
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: /* No Clobbers */);
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}
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}
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#endif /* !__ASSEMBLY__ */
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/*
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* Cache Operations available on all MIPS processors with R4000-style caches
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*/
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#define INDEX_INVALIDATE_I 0x00
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#define INDEX_WRITEBACK_INV_D 0x01
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#define INDEX_LOAD_TAG_I 0x04
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#define INDEX_LOAD_TAG_D 0x05
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#define INDEX_STORE_TAG_I 0x08
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#define INDEX_STORE_TAG_D 0x09
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#if defined(CONFIG_CPU_LOONGSON2)
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#define HIT_INVALIDATE_I 0x00
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#else
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#define HIT_INVALIDATE_I 0x10
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#endif
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#define HIT_INVALIDATE_D 0x11
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#define HIT_WRITEBACK_INV_D 0x15
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/*
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* R4000-specific cacheops
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*/
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#define CREATE_DIRTY_EXCL_D 0x0d
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#define FILL 0x14
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#define HIT_WRITEBACK_I 0x18
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#define HIT_WRITEBACK_D 0x19
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/*
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* R4000SC and R4400SC-specific cacheops
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*/
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#define INDEX_INVALIDATE_SI 0x02
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#define INDEX_WRITEBACK_INV_SD 0x03
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#define INDEX_LOAD_TAG_SI 0x06
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#define INDEX_LOAD_TAG_SD 0x07
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#define INDEX_STORE_TAG_SI 0x0A
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#define INDEX_STORE_TAG_SD 0x0B
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#define CREATE_DIRTY_EXCL_SD 0x0f
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#define HIT_INVALIDATE_SI 0x12
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#define HIT_INVALIDATE_SD 0x13
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#define HIT_WRITEBACK_INV_SD 0x17
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#define HIT_WRITEBACK_SD 0x1b
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#define HIT_SET_VIRTUAL_SI 0x1e
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#define HIT_SET_VIRTUAL_SD 0x1f
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/*
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* R5000-specific cacheops
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*/
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#define R5K_PAGE_INVALIDATE_S 0x17
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/*
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* RM7000-specific cacheops
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*/
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#define PAGE_INVALIDATE_T 0x16
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/*
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* R10000-specific cacheops
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*
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* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
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* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
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*/
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#define INDEX_WRITEBACK_INV_S 0x03
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#define INDEX_LOAD_TAG_S 0x07
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#define INDEX_STORE_TAG_S 0x0B
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#define HIT_INVALIDATE_S 0x13
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#define CACHE_BARRIER 0x14
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#define HIT_WRITEBACK_INV_S 0x17
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#define INDEX_LOAD_DATA_I 0x18
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#define INDEX_LOAD_DATA_D 0x19
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#define INDEX_LOAD_DATA_S 0x1b
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#define INDEX_STORE_DATA_I 0x1c
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#define INDEX_STORE_DATA_D 0x1d
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#define INDEX_STORE_DATA_S 0x1f
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#endif /* __ASM_CACHEOPS_H */
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