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u-boot-megous/doc/README.440-DDR-performance
Stefan Roese a2c95a7224 PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance 
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
2006-07-28 18:34:58 +02:00

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