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63779b2407
The timer being used by this driver may have already been used by first stage bootloader (e.g. ATF/preloader), and it's settings may differ from what this driver is going to use. This may cause issues, such as inaccurate timer frequency due to incorrect clock divider. This patch adds the initialization code to avoid them. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
96 lines
2.0 KiB
C
96 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek timer driver
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#define MTK_GPT4_CTRL 0x40
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#define MTK_GPT4_CLK 0x44
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#define MTK_GPT4_CNT 0x48
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#define GPT4_ENABLE BIT(0)
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#define GPT4_CLEAR BIT(1)
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#define GPT4_FREERUN GENMASK(5, 4)
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#define GPT4_CLK_SYS 0x0
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#define GPT4_CLK_DIV1 0x0
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struct mtk_timer_priv {
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void __iomem *base;
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};
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static u64 mtk_timer_get_count(struct udevice *dev)
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{
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struct mtk_timer_priv *priv = dev_get_priv(dev);
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u32 val = readl(priv->base + MTK_GPT4_CNT);
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return timer_conv_64(val);
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}
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static int mtk_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct mtk_timer_priv *priv = dev_get_priv(dev);
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struct clk clk, parent;
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -ENOENT;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_get_by_index(dev, 1, &parent);
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if (!ret) {
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ret = clk_set_parent(&clk, &parent);
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if (ret)
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return ret;
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}
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uc_priv->clock_rate = clk_get_rate(&clk);
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if (!uc_priv->clock_rate)
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return -EINVAL;
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/*
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* Initialize the timer:
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* 1. set clock source to system clock with clock divider setting to 1
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* 2. set timer mode to free running
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* 3. reset timer counter to 0 then enable the timer
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*/
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writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK);
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writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE,
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priv->base + MTK_GPT4_CTRL);
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return 0;
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}
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static const struct timer_ops mtk_timer_ops = {
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.get_count = mtk_timer_get_count,
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};
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static const struct udevice_id mtk_timer_ids[] = {
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{ .compatible = "mediatek,timer" },
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{ .compatible = "mediatek,mt6577-timer" },
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{ }
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};
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U_BOOT_DRIVER(mtk_timer) = {
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.name = "mtk_timer",
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.id = UCLASS_TIMER,
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.of_match = mtk_timer_ids,
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.priv_auto = sizeof(struct mtk_timer_priv),
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.probe = mtk_timer_probe,
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.ops = &mtk_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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