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https://xff.cz/git/u-boot/
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dfd0adc2f6
Synchronise device tree with linux v6.0-rc1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017~2018 NXP
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
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#define __DT_BINDINGS_CLOCK_IMX7ULP_H
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/* SCG1 */
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#define IMX7ULP_CLK_DUMMY 0
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#define IMX7ULP_CLK_ROSC 1
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#define IMX7ULP_CLK_SOSC 2
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#define IMX7ULP_CLK_FIRC 3
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#define IMX7ULP_CLK_SPLL_PRE_SEL 4
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#define IMX7ULP_CLK_SPLL_PRE_DIV 5
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#define IMX7ULP_CLK_SPLL 6
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#define IMX7ULP_CLK_SPLL_POST_DIV1 7
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#define IMX7ULP_CLK_SPLL_POST_DIV2 8
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#define IMX7ULP_CLK_SPLL_PFD0 9
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#define IMX7ULP_CLK_SPLL_PFD1 10
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#define IMX7ULP_CLK_SPLL_PFD2 11
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#define IMX7ULP_CLK_SPLL_PFD3 12
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#define IMX7ULP_CLK_SPLL_PFD_SEL 13
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#define IMX7ULP_CLK_SPLL_SEL 14
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#define IMX7ULP_CLK_APLL_PRE_SEL 15
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#define IMX7ULP_CLK_APLL_PRE_DIV 16
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#define IMX7ULP_CLK_APLL 17
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#define IMX7ULP_CLK_APLL_POST_DIV1 18
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#define IMX7ULP_CLK_APLL_POST_DIV2 19
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#define IMX7ULP_CLK_APLL_PFD0 20
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#define IMX7ULP_CLK_APLL_PFD1 21
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#define IMX7ULP_CLK_APLL_PFD2 22
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#define IMX7ULP_CLK_APLL_PFD3 23
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#define IMX7ULP_CLK_APLL_PFD_SEL 24
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#define IMX7ULP_CLK_APLL_SEL 25
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#define IMX7ULP_CLK_UPLL 26
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#define IMX7ULP_CLK_SYS_SEL 27
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#define IMX7ULP_CLK_CORE_DIV 28
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#define IMX7ULP_CLK_BUS_DIV 29
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#define IMX7ULP_CLK_PLAT_DIV 30
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#define IMX7ULP_CLK_DDR_SEL 31
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#define IMX7ULP_CLK_DDR_DIV 32
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#define IMX7ULP_CLK_NIC_SEL 33
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#define IMX7ULP_CLK_NIC0_DIV 34
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#define IMX7ULP_CLK_GPU_DIV 35
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#define IMX7ULP_CLK_NIC1_DIV 36
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#define IMX7ULP_CLK_NIC1_BUS_DIV 37
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#define IMX7ULP_CLK_NIC1_EXT_DIV 38
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/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
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#define IMX7ULP_CLK_MIPI_PLL 39
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#define IMX7ULP_CLK_SIRC 40
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#define IMX7ULP_CLK_SOSC_BUS_CLK 41
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#define IMX7ULP_CLK_FIRC_BUS_CLK 42
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#define IMX7ULP_CLK_SPLL_BUS_CLK 43
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#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
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#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
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#define IMX7ULP_CLK_CORE 46
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#define IMX7ULP_CLK_HSRUN_CORE 47
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#define IMX7ULP_CLK_SCG1_END 48
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/* PCC2 */
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#define IMX7ULP_CLK_DMA1 0
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#define IMX7ULP_CLK_RGPIO2P1 1
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#define IMX7ULP_CLK_FLEXBUS 2
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#define IMX7ULP_CLK_SEMA42_1 3
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#define IMX7ULP_CLK_DMA_MUX1 4
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#define IMX7ULP_CLK_CAAM 6
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#define IMX7ULP_CLK_LPTPM4 7
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#define IMX7ULP_CLK_LPTPM5 8
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#define IMX7ULP_CLK_LPIT1 9
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#define IMX7ULP_CLK_LPSPI2 10
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#define IMX7ULP_CLK_LPSPI3 11
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#define IMX7ULP_CLK_LPI2C4 12
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#define IMX7ULP_CLK_LPI2C5 13
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#define IMX7ULP_CLK_LPUART4 14
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#define IMX7ULP_CLK_LPUART5 15
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#define IMX7ULP_CLK_FLEXIO1 16
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#define IMX7ULP_CLK_USB0 17
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#define IMX7ULP_CLK_USB1 18
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#define IMX7ULP_CLK_USB_PHY 19
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#define IMX7ULP_CLK_USB_PL301 20
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#define IMX7ULP_CLK_USDHC0 21
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#define IMX7ULP_CLK_USDHC1 22
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#define IMX7ULP_CLK_WDG1 23
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#define IMX7ULP_CLK_WDG2 24
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#define IMX7ULP_CLK_PCC2_END 25
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/* PCC3 */
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#define IMX7ULP_CLK_LPTPM6 0
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#define IMX7ULP_CLK_LPTPM7 1
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#define IMX7ULP_CLK_LPI2C6 2
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#define IMX7ULP_CLK_LPI2C7 3
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#define IMX7ULP_CLK_LPUART6 4
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#define IMX7ULP_CLK_LPUART7 5
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#define IMX7ULP_CLK_VIU 6
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#define IMX7ULP_CLK_DSI 7
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#define IMX7ULP_CLK_LCDIF 8
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#define IMX7ULP_CLK_MMDC 9
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#define IMX7ULP_CLK_PCTLC 10
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#define IMX7ULP_CLK_PCTLD 11
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#define IMX7ULP_CLK_PCTLE 12
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#define IMX7ULP_CLK_PCTLF 13
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#define IMX7ULP_CLK_GPU3D 14
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#define IMX7ULP_CLK_GPU2D 15
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#define IMX7ULP_CLK_PCC3_END 16
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/* SMC1 */
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#define IMX7ULP_CLK_ARM 0
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#define IMX7ULP_CLK_SMC1_END 1
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#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
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