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https://xff.cz/git/u-boot/
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798cd708d5
Replace clrsetbits on ODR register (2 operations: one read + one write) by writing on the correct bit (SET or RESET) of the BSRR register (only 1 write operation). Moreover this register if safe for simultaneous access by 2 master on the bus. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/stm32.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#define STM32_GPIOS_PER_BANK 16
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#define MODE_BITS(gpio_pin) (gpio_pin * 2)
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#define MODE_BITS_MASK 3
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#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
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static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int bits_index = MODE_BITS(offset);
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int mask = MODE_BITS_MASK << bits_index;
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clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
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return 0;
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}
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static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int bits_index = MODE_BITS(offset);
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int mask = MODE_BITS_MASK << bits_index;
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clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
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writel(BSRR_BIT(offset, value), ®s->bsrr);
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return 0;
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}
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static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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return readl(®s->idr) & BIT(offset) ? 1 : 0;
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}
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static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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writel(BSRR_BIT(offset, value), ®s->bsrr);
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return 0;
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}
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static const struct dm_gpio_ops gpio_stm32_ops = {
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.direction_input = stm32_gpio_direction_input,
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.direction_output = stm32_gpio_direction_output,
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.get_value = stm32_gpio_get_value,
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.set_value = stm32_gpio_set_value,
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};
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static int gpio_stm32_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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const char *name;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = (struct stm32_gpio_regs *)addr;
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name = dev_read_string(dev, "st,bank-name");
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if (!name)
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return -EINVAL;
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uc_priv->bank_name = name;
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uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
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STM32_GPIOS_PER_BANK);
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debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
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uc_priv->bank_name);
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#ifdef CONFIG_CLK
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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debug("clock enabled for device %s\n", dev->name);
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#endif
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return 0;
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}
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static const struct udevice_id stm32_gpio_ids[] = {
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{ .compatible = "st,stm32-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_stm32) = {
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.name = "gpio_stm32",
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.id = UCLASS_GPIO,
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.of_match = stm32_gpio_ids,
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.probe = gpio_stm32_probe,
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.ops = &gpio_stm32_ops,
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.flags = DM_FLAG_PRE_RELOC | DM_UC_FLAG_SEQ_ALIAS,
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.priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
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};
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