There's no other way to load bitstream file to Zynq 7000 via SPL
otherwise, and SPL just reports:
zynq_validate_bitstream: Bitstream is not validated yet (diff 6c)
spl_fit_upload_fpga: Cannot load the image to the FPGA
This is similar to code in boot/image-board.c
Signed-off-by: Ondrej Jirman <megi@xff.cz>
ebfe55ad41