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spl: Try loading bitstream first, before falling back to fpga_load

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There's no other way to load bitstream file to Zynq 7000 via SPL
otherwise, and SPL just reports:

  zynq_validate_bitstream: Bitstream is not validated yet (diff 6c)
  spl_fit_upload_fpga: Cannot load the image to the FPGA

This is similar to code in boot/image-board.c

Signed-off-by: Ondrej Jirman <megi@xff.cz>
This commit is contained in:
Ondrej Jirman
2024-04-25 16:46:13 +02:00
parent 1600fdea6d
commit ebfe55ad41
1 changed files with 5 additions and 2 deletions
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7
common/spl/spl_fit.c
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@@ -613,8 +613,11 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node,
compatible);
}
ret = fpga_load(devnum, (void *)fpga_image->load_addr,
fpga_image->size, BIT_FULL, flags);
ret = fpga_loadbitstream(devnum, (void *)fpga_image->load_addr,
fpga_image->size, BIT_FULL);
if (ret)
ret = fpga_load(devnum, (void *)fpga_image->load_addr,
fpga_image->size, BIT_FULL, flags);
if (ret) {
printf("%s: Cannot load the image to the FPGA\n", __func__);
return ret;