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b80ec768a3
On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
19 lines
431 B
Plaintext
19 lines
431 B
Plaintext
menu "i.MX8ULP DDR controllers"
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depends on ARCH_IMX8ULP
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config IMX8ULP_DRAM
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bool "imx8m dram"
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config IMX8ULP_DRAM_PHY_PLL_BYPASS
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bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
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depends on IMX8ULP_DRAM
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config SAVED_DRAM_TIMING_BASE
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hex "Define the base address for saved dram timing"
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help
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The DRAM config timing data need to be saved into sram
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for low power use.
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default 0x2006c000
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endmenu
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