Simon Goldschmidt d6d383ca27 arm: socfpga: provide default SPL_SIZE_LIMIT for gen5 ...

This provides an SPL_SIZE_LIMIT that makes the build check that the SPL
binary loaded from flash fits into the SRAM (64 KiB) and leaves enough
room for global data, heap  and stack (512 bytes assumed stack usage).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

2019-06-14 12:41:26 +02:00

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include/mach

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board.c

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clock_manager_arria10.c

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clock_manager_gen5.c

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clock_manager_s10.c

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clock_manager.c

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fpga_manager.c

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freeze_controller.c

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Kconfig

arm: socfpga: provide default SPL_SIZE_LIMIT for gen5

2019-06-14 12:41:26 +02:00

mailbox_s10.c

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Makefile

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misc_arria10.c

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misc_gen5.c

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misc_s10.c

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misc.c

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mmu-arm64_s10.c

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pinmux_arria10.c

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qts-filter.sh

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reset_manager_arria10.c

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reset_manager_gen5.c

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reset_manager_s10.c

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reset_manager.c

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scan_manager.c

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spl_a10.c

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spl_gen5.c

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spl_s10.c

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system_manager_gen5.c

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system_manager_s10.c

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timer_s10.c

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timer.c

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wrap_iocsr_config.c

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wrap_pinmux_config_s10.c

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wrap_pinmux_config.c

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wrap_pll_config_s10.c

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wrap_pll_config.c

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wrap_sdram_config.c

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