Daniel Schwierzeck 5ef337a037 MIPS: cache: make index base address configurable ...

The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

2018-09-22 21:02:03 +02:00

..

arc

arch: types.h: factor out fixed width typedefs to int-ll64.h

2018-09-10 20:48:16 -04:00

arm

Merge git://git.denx.de/u-boot-imx

2018-09-19 20:35:27 -04:00

m68k

m68k: ColdFire mcf5441x, add eSDHC support

2018-09-16 00:01:13 +02:00

microblaze

arch: types.h: factor out fixed width typedefs to int-ll64.h

2018-09-10 20:48:16 -04:00

mips

MIPS: cache: make index base address configurable

2018-09-22 21:02:03 +02:00

nds32

arch: types.h: factor out fixed width typedefs to int-ll64.h

2018-09-10 20:48:16 -04:00

nios2

.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore

2018-06-18 14:43:12 -04:00

powerpc

misc: Add MPC83xx serdes driver

2018-09-18 08:12:21 -06:00

riscv

arch: types.h: factor out fixed width typedefs to int-ll64.h

2018-09-10 20:48:16 -04:00

sandbox

test: Add tests for CPU uclass

2018-09-18 08:12:21 -06:00

sh

sh: tmu: Zap get_tbclk and timer_read_counter

2018-09-15 03:19:07 +02:00

x86

x86: cpu: add docstring to scu_ipc_command()

2018-09-17 17:35:53 +08:00

xtensa

arch: types.h: factor out fixed width typedefs to int-ll64.h

2018-09-10 20:48:16 -04:00

.gitignore

…

Kconfig

sandbox: Enable bitrev library build

2018-09-18 00:01:18 -06:00