mirror of
https://xff.cz/git/u-boot/
synced 2025-10-31 18:35:42 +01:00
203e94f6c9
At present we have three states for the environment, numbered 0, 1 and 2. Add an enum to record this to avoid open-coded values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
113 lines
2.7 KiB
C
113 lines
2.7 KiB
C
/* Copyright 2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <console.h>
|
|
#include <environment.h>
|
|
#include <ns16550.h>
|
|
#include <malloc.h>
|
|
#include <mmc.h>
|
|
#include <nand.h>
|
|
#include <i2c.h>
|
|
#include <fsl_esdhc.h>
|
|
#include <spi_flash.h>
|
|
#include "../common/spl.h"
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
phys_size_t get_effective_memsize(void)
|
|
{
|
|
return CONFIG_SYS_L2_SIZE;
|
|
}
|
|
|
|
void board_init_f(ulong bootflag)
|
|
{
|
|
u32 plat_ratio;
|
|
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
|
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
|
|
|
|
console_init_f();
|
|
|
|
/* Clock configuration to access CPLD using IFC(GPCM) */
|
|
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
|
|
|
|
#ifdef CONFIG_TARGET_P1010RDB_PB
|
|
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
|
|
#endif
|
|
|
|
/* initialize selected port with appropriate baud rate */
|
|
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
|
plat_ratio >>= 1;
|
|
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
|
|
|
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
|
gd->bus_clk / 16 / CONFIG_BAUDRATE);
|
|
|
|
#ifdef CONFIG_SPL_MMC_BOOT
|
|
puts("\nSD boot...\n");
|
|
#elif defined(CONFIG_SPL_SPI_BOOT)
|
|
puts("\nSPI Flash boot...\n");
|
|
#endif
|
|
/* copy code to RAM and jump to it - this should not return */
|
|
/* NOTE - code has to be copied out of NAND buffer before
|
|
* other blocks can be read.
|
|
*/
|
|
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
|
|
}
|
|
|
|
void board_init_r(gd_t *gd, ulong dest_addr)
|
|
{
|
|
/* Pointer is writable since we allocated a register for it */
|
|
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
|
|
bd_t *bd;
|
|
|
|
memset(gd, 0, sizeof(gd_t));
|
|
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
|
|
memset(bd, 0, sizeof(bd_t));
|
|
gd->bd = bd;
|
|
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
|
|
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
|
|
|
|
arch_cpu_init();
|
|
get_clocks();
|
|
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
|
|
CONFIG_SPL_RELOC_MALLOC_SIZE);
|
|
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
|
|
|
|
#ifndef CONFIG_SPL_NAND_BOOT
|
|
env_init();
|
|
#endif
|
|
#ifdef CONFIG_SPL_MMC_BOOT
|
|
mmc_initialize(bd);
|
|
#endif
|
|
|
|
/* relocate environment function pointers etc. */
|
|
#ifdef CONFIG_SPL_NAND_BOOT
|
|
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
|
(uchar *)CONFIG_ENV_ADDR);
|
|
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
|
|
gd->env_valid = ENV_VALID;
|
|
#else
|
|
env_relocate();
|
|
#endif
|
|
|
|
i2c_init_all();
|
|
|
|
dram_init();
|
|
#ifdef CONFIG_SPL_NAND_BOOT
|
|
puts("\nTertiary program loader running in sram...");
|
|
#else
|
|
puts("\nSecond program loader running in sram...");
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPL_MMC_BOOT
|
|
mmc_boot();
|
|
#elif defined(CONFIG_SPL_SPI_BOOT)
|
|
fsl_spi_boot();
|
|
#elif defined(CONFIG_SPL_NAND_BOOT)
|
|
nand_boot();
|
|
#endif
|
|
}
|