Michal Simek 9b7aac7536 clk: zynq: Add dummy clock enable function ...

A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c11 ("clk: fixed_rate: add dummy enable() function").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

2021-02-23 14:56:59 +01:00

4.2 KiB

Raw Blame History

View Raw