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u-boot-megous/common
Ondrej Jirman ebfe55ad41 spl: Try loading bitstream first, before falling back to fpga_load
There's no other way to load bitstream file to Zynq 7000 via SPL
otherwise, and SPL just reports:

  zynq_validate_bitstream: Bitstream is not validated yet (diff 6c)
  spl_fit_upload_fpga: Cannot load the image to the FPGA

This is similar to code in boot/image-board.c

Signed-off-by: Ondrej Jirman <megi@xff.cz>
2024-07-05 17:41:45 +02:00
..
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2022-11-02 08:42:03 +01:00
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