Previously we have known that R40 has a configuration register for its
rank 1, which allows different configuration than rank 0. Reverse
engineering of newest libdram of A64 from Allwinner shows that A64 has
this register too. It's bit 0 (which enables dual rank in rank 0
configuration register) means a dedicated rank size setup is used for
rank 1.
Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB
rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank
DRAM support necessary.
Add this support. As we have gained knowledge of asymmetric dual rank,
we can now allow R40 dual rank memory setup to work too.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
When the user has a volume key pressed volume_key variable will
contain either value 'down' or 'up', otherwise it will be empty.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Orange Pi 3 has 2 GiB of DRAM, that sometime get misdetected
as 4 GiB, due to false negative result from mctl_mem_matches()
when detecting number of column address bits. This leads to
u-boot detecting more address bits than there are and the
boot process hangs shortly after.
In mctl_mem_matches() we need to wait for each write to finish,
separately. Without this, the check is not reliable for some
unknown reason, probably having to do with unpredictable memory
access ordering.
Patch was made with help from André Przywara, who noticed that
my original idea about detection failing due to read-back from
cache without involving DRAM was false, because data cache is
still of at the time of the DRAM size autodetection.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Cc: André Przywara <andre.przywara@arm.com>
This is useful for boot scripts to be able to decide whether to
boot or not and whether to notify the user of what is wrong.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Device tree is slightly different from Linux kernel one, because of
different ABI for display timings between u-boot and Linux.
Signed-off-by: Ondrej Jirman <megous@megous.com>
- Enable LVDS pins (PD18-PD27)
- De-assert LVDS interface reset line
- Enable sunxi_lcd platform device for A83T
- Really disable all interrupts
- A83T does have only a simple clock gate for TCON0 clock
(no need to select source)
- Lifted some analog circuitry setup magic from the Linux driver
Signed-off-by: Ondrej Jirman <megous@megous.com>
A83T SoC has PLL_DE at pll9. Change the name to make it less
confusing when we'll add DE2 support for A83T.
Signed-off-by: Ondrej Jirman <megous@megous.com>
- so that we can show it quickly and do stuff "in the background"
before accepting input from the user
Signed-off-by: Ondrej Jirman <megous@megous.com>
Shows a menu of items that can be controlled using touch panel.
This is useful for touch based devices like tablets to select
alternative boot options (multi-boot).
Signed-off-by: Ondrej Jirman <megous@megous.com>
We don't have DM support for PMIC/GPIO/regulators, so this needs
to be handled via config options and some custom board initialization
code for now.
Signed-off-by: Ondrej Jirman <megous@megous.com>
To enable LDO on GPIO0 and set it to required voltage define
CONFIG_AXP_GPIO_LDO0_VOLT=<mV> in your defconfig. Eg. <mV> can
be 3100 for 3.1V.
Signed-off-by: Ondrej Jirman <megous@megous.com>
