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clk: rockchip: Static clock settings for VOPs on Pinephone Pro

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cpll in U-Boot runs at 384 MHz, set various VOP related clocks to produce
roughly 400 and 100 MHz just like in Linux.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
This commit is contained in:
Ondrej Jirman
2022-09-05 19:54:53 +02:00
parent eef970222b
commit ea58d74af8
1 changed files with 22 additions and 0 deletions
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22
drivers/clk/rockchip/clk_rk3399.c
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@@ -1472,6 +1472,28 @@ static void rkclk_init(struct rockchip_cru *cru)
pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
if (of_machine_is_compatible("pine64,pinephone-pro")) {
/*
* VOP clocks
*
* cpll (800 MHz) -> aclk (400 MHz) -> hclk (100 MHz)
* gpll (594 MHz) -> dclk (74.25 MHz)
*
* DCLK_VOP1 ?
*
* CRU_CLKSEL_CON47 vop0
* CRU_CLKSEL_CON48 vop1
*/
rk_clrsetreg(&cru->clksel_con[47], 0xffff, 0x340); // aclk/1 hclk/4
rk_clrsetreg(&cru->clksel_con[48], 0xffff, 0x340); // aclk/1 hclk/4
rk_clrsetreg(&cru->clksel_con[49], 0xffff, 0x207); // gpll/8
rk_clrsetreg(&cru->clksel_con[50], 0xffff, 0x207); // gpll/8
// vop1 (BIT(13) | BIT(11) | BIT(10))
// vop0 (BIT(12) | BIT(9) | BIT(8))
//rk_setreg(&cru->clkgate_con[10], BIT(12) | BIT(9) | BIT(8));
}
} }
static int rk3399_clk_probe(struct udevice *dev) static int rk3399_clk_probe(struct udevice *dev)