From ea58d74af8ee1fba77008bcbce4b66c56738c9ea Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 5 Sep 2022 19:54:53 +0200 Subject: [PATCH] clk: rockchip: Static clock settings for VOPs on Pinephone Pro cpll in U-Boot runs at 384 MHz, set various VOP related clocks to produce roughly 400 and 100 MHz just like in Linux. Signed-off-by: Ondrej Jirman --- drivers/clk/rockchip/clk_rk3399.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 1c3d649db25..1434ee74d2b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1472,6 +1472,28 @@ static void rkclk_init(struct rockchip_cru *cru) pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); + + if (of_machine_is_compatible("pine64,pinephone-pro")) { + /* + * VOP clocks + * + * cpll (800 MHz) -> aclk (400 MHz) -> hclk (100 MHz) + * gpll (594 MHz) -> dclk (74.25 MHz) + * + * DCLK_VOP1 ? + * + * CRU_CLKSEL_CON47 vop0 + * CRU_CLKSEL_CON48 vop1 + */ + rk_clrsetreg(&cru->clksel_con[47], 0xffff, 0x340); // aclk/1 hclk/4 + rk_clrsetreg(&cru->clksel_con[48], 0xffff, 0x340); // aclk/1 hclk/4 + rk_clrsetreg(&cru->clksel_con[49], 0xffff, 0x207); // gpll/8 + rk_clrsetreg(&cru->clksel_con[50], 0xffff, 0x207); // gpll/8 + + // vop1 (BIT(13) | BIT(11) | BIT(10)) + // vop0 (BIT(12) | BIT(9) | BIT(8)) + //rk_setreg(&cru->clkgate_con[10], BIT(12) | BIT(9) | BIT(8)); + } } static int rk3399_clk_probe(struct udevice *dev)