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riscv: dts: sophgo: Add spi nor flash controller node

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Add spi nor flash controller node for cv18xx SoCs

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Kongyang Liu
2024-04-20 15:08:24 +08:00
committed by Leo Yu-Chi Liang
parent 6c75bea76a
commit df0bfaa136
2 changed files with 30 additions and 0 deletions
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13
arch/riscv/dts/cv1800b-milkv-duo.dts
View File

@@ -46,6 +46,19 @@
no-sdio;
};
&spif {
status = "okay";
spiflash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <75000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
};
};
&uart0 {
status = "okay";
};

17
arch/riscv/dts/cv18xx.dtsi
View File

@@ -66,6 +66,13 @@
#clock-cells = <0x0>;
};
spif_clk: spi-flash-clock {
compatible = "fixed-clock";
clock-frequency = <300000000>;
clock-output-names = "spif_clk";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -220,6 +227,16 @@
status = "disabled";
};
spif: spi-nor@10000000 {
compatible = "sophgo,cv1800b-spif";
reg = <0x10000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&spif_clk>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;