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Kconfig: Remove trailing whitespace in its prompt

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All errors are generated by ./tools/qconfig.py -b -j8 -i whatever.
Error look like this:
warning: SPL_CLK_CCF (defined at drivers/clk/Kconfig:59) has leading or
trailing whitespace in its prompt

Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Michal Simek
2024-04-16 08:55:15 +02:00
committed by Tom Rini
parent 6e316e3f39
commit d20bcbaa65
2 changed files with 6 additions and 6 deletions
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10
drivers/clk/Kconfig
View File

@@ -57,27 +57,27 @@ config CLK_BOSTON
Enable this to support the clocks
config SPL_CLK_CCF
bool "SPL Common Clock Framework [CCF] support "
bool "SPL Common Clock Framework [CCF] support"
depends on SPL
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's SPL.
config SPL_CLK_COMPOSITE_CCF
bool "SPL Common Clock Framework [CCF] composite clk support "
bool "SPL Common Clock Framework [CCF] composite clk support"
depends on SPL_CLK_CCF
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] composite code in U-Boot's SPL.
config CLK_CCF
bool "Common Clock Framework [CCF] support "
bool "Common Clock Framework [CCF] support"
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's clock driver.
config CLK_COMPOSITE_CCF
bool "Common Clock Framework [CCF] composite clk support "
bool "Common Clock Framework [CCF] composite clk support"
depends on CLK_CCF
help
Enable this option if you want to (re-)use the Linux kernel's Common
@@ -164,7 +164,7 @@ config CLK_OCTEON
Enable this to support the clocks on Octeon MIPS platforms.
config SANDBOX_CLK_CCF
bool "Sandbox Common Clock Framework [CCF] support "
bool "Sandbox Common Clock Framework [CCF] support"
depends on SANDBOX
select CLK_CCF
help

2
drivers/ddr/imx/imx8ulp/Kconfig
View File

@@ -5,7 +5,7 @@ config IMX8ULP_DRAM
bool "imx8m dram"
config IMX8ULP_DRAM_PHY_PLL_BYPASS
bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK"
depends on IMX8ULP_DRAM
config SAVED_DRAM_TIMING_BASE