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mx7ulp: scg: Remove unnused scg_a7_apll_init()

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scg_a7_apll_init() is not called anywhere, so remove such dead code

Signed-off-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Fabio Estevam
2019-11-05 09:47:53 -03:00
committed by Stefano Babic
parent 0619af0942
commit d136eb9bfe
2 changed files with 0 additions and 62 deletions
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1
arch/arm/include/asm/arch-mx7ulp/scg.h
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@@ -331,7 +331,6 @@ u32 decode_pll(enum pll_clocks pll);
void scg_a7_rccr_init(void);
void scg_a7_spll_init(void);
void scg_a7_ddrclk_init(void);
void scg_a7_apll_init(void);
void scg_a7_firc_init(void);
void scg_a7_nicclk_init(void);
void scg_a7_sys_clk_sel(enum scg_sys_src clk);

61
arch/arm/mach-imx/mx7ulp/scg.c
View File

@@ -949,67 +949,6 @@ void scg_a7_ddrclk_init(void)
/* Clock source is System OSC <<0 */
#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
/*
* A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
* system PLL is sourced from APLL,
* APLL clock source is system OSC (24MHz)
*/
#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
SCG1_APLL_CFG_POSTDIV1_NUM | \
(22 << SCG_PLL_CFG_MULT_SHIFT) | \
SCG1_APLL_CFG_PFDSEL_NUM | \
SCG1_APLL_CFG_PREDIV_NUM | \
SCG1_APLL_CFG_BYPASS_NUM | \
SCG1_APLL_CFG_PLLSEL_NUM | \
SCG1_APLL_CFG_CLKSRC_NUM)
/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
#define SCG1_APLL_PFD0_FRAC_NUM (27)
void scg_a7_apll_init(void)
{
u32 val = 0;
/* Disable A7 Auxiliary PLL */
val = readl(&scg1_regs->apllcsr);
val &= ~SCG_APLL_CSR_APLLEN_MASK;
writel(val, &scg1_regs->apllcsr);
/* Gate off A7 APLL PFD0 ~ PDF4 */
val = readl(&scg1_regs->apllpfd);
val |= 0x80808080;
writel(val, &scg1_regs->apllpfd);
/* ================ A7 APLL Configuration Start ============== */
/* Configure A7 Auxiliary PLL */
writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
/* Enable A7 Auxiliary PLL */
val = readl(&scg1_regs->apllcsr);
val |= SCG_APLL_CSR_APLLEN_MASK;
writel(val, &scg1_regs->apllcsr);
/* Wait for A7 APLL clock ready */
while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
;
/* Configure A7 APLL PFD0 */
val = readl(&scg1_regs->apllpfd);
val &= ~SCG_PLL_PFD0_FRAC_MASK;
val |= SCG1_APLL_PFD0_FRAC_NUM;
writel(val, &scg1_regs->apllpfd);
/* Un-gate A7 APLL PFD0 */
val = readl(&scg1_regs->apllpfd);
val &= ~SCG_PLL_PFD0_GATE_MASK;
writel(val, &scg1_regs->apllpfd);
/* Wait for A7 APLL PFD0 clock being valid */
while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
;
}
/* SCG1(A7) FIRC DIV configurations */
/* Disable FIRC DIV3 */
#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)