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mmc: rockchip_dw_mmc: Fix get_mmc_clk return value

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The get_mmc_clk ops is expected to set a clock rate and return the
configured rate as an unsigned value. However, if clk_set_rate fails,
e.g. using a fixed rate clock, a negative error value is returned.

The mmc core will treat this as a valid unsigned rate and tries to
configure a divider based on this bogus clock rate.

Use 0 as the return value when setting clock rate fails, the mmc core
will configure to use bypass mode instead of using a bogus divider.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
2023-03-14 00:38:32 +00:00
committed by Kever Yang
parent 42a502ad1a
commit d11f0dac30
1 changed files with 1 additions and 1 deletions
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2
drivers/mmc/rockchip_dw_mmc.c
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@@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
ret = clk_set_rate(&priv->clk, freq);
if (ret < 0) {
debug("%s: err=%d\n", __func__, ret);
return ret;
return 0;
}
return freq;