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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

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- Two rswitch fixes and a clock fix
This commit is contained in:
Tom Rini
2024-12-21 09:45:30 -06:00
parent 5c8ef70f08 fa0f9e83a0
commit cfe57427c2
3 changed files with 6 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/clk/renesas/r8a779h0-cpg-mssr.c
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@@ -39,7 +39,6 @@ enum clk_ids {
CLK_PLL6, CLK_PLL6,
CLK_PLL7, CLK_PLL7,
CLK_PLL1_DIV2, CLK_PLL1_DIV2,
CLK_PLL2_DIV2,
CLK_PLL3_DIV2, CLK_PLL3_DIV2,
CLK_PLL4_DIV2, CLK_PLL4_DIV2,
CLK_PLL4_DIV5, CLK_PLL4_DIV5,
@@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1),
@@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
DEF_RATE(".oco", CLK_OCO, 32768), DEF_RATE(".oco", CLK_OCO, 32768),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0),
DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8),
DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32),
DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40),
DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1),

1
drivers/net/rswitch.c
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@@ -837,6 +837,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len)
/* Update TX descriptor */ /* Update TX descriptor */
rswitch_flush_dcache((uintptr_t)packet, len); rswitch_flush_dcache((uintptr_t)packet, len);
rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
memset(desc, 0x0, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc));
desc->die_dt = DT_FSINGLE; desc->die_dt = DT_FSINGLE;
desc->info_ds = len; desc->info_ds = len;

2
net/Kconfig
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@@ -90,7 +90,7 @@ config TFTP_WINDOWSIZE
config TFTP_TSIZE config TFTP_TSIZE
bool "Track TFTP transfers based on file size option" bool "Track TFTP transfers based on file size option"
depends on CMD_TFTPBOOT depends on CMD_TFTPBOOT
default y if (ARCH_OMAP2PLUS || ARCH_K3) default y if (ARCH_OMAP2PLUS || ARCH_K3 || ARCH_RENESAS)
help help
By default, TFTP progress bar is increased for each received UDP By default, TFTP progress bar is increased for each received UDP
frame, which can lead into long time being spent for sending frame, which can lead into long time being spent for sending