From 08806a6e5224e2500f54c2c29acbb6724fe7f5a9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 Dec 2024 01:04:08 +0100 Subject: [PATCH 1/3] clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Early revisions of the R-Car V4M Series Hardware User’s Manual contained an incorrect formula for the CPU core clocks: ZCnφ = (PLL2VCO x 1/2) x mult/32 Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the parent clock. In Rev.0.70 of the documentation, the formula was corrected to: ZCnφ = (PLL2VCO x 1/4) x mult/32 As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2, the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4 (and Gen3) SoCs. Ported from Linux commit 92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks") Reported-by: Vinh Nguyen Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be Signed-off-by: Marek Vasut --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 2e98e262fb0..70fa8ff2871 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -39,7 +39,6 @@ enum clk_ids { CLK_PLL6, CLK_PLL7, CLK_PLL1_DIV2, - CLK_PLL2_DIV2, CLK_PLL3_DIV2, CLK_PLL4_DIV2, CLK_PLL4_DIV5, @@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), @@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ - DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), - DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), - DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), - DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0), + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8), + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32), + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40), DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), From 9899a6a7506c99c5c9e9265b8dbafb716089b6d9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 18 Dec 2024 20:41:28 +0100 Subject: [PATCH 2/3] net: renesas: Enable TFTP_TSIZE on all Renesas hardware TFTP transfer size can be used to re-size the TFTP progress bar on single line based on the server reported file size. Enable it by default for Renesas hardware to avoid long scrolling walls of '#' character during long TFTP transfers. Signed-off-by: Marek Vasut --- net/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/Kconfig b/net/Kconfig index 76ab7d91eeb..489ac19f8d1 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -90,7 +90,7 @@ config TFTP_WINDOWSIZE config TFTP_TSIZE bool "Track TFTP transfers based on file size option" depends on CMD_TFTPBOOT - default y if (ARCH_OMAP2PLUS || ARCH_K3) + default y if (ARCH_OMAP2PLUS || ARCH_K3 || ARCH_RENESAS) help By default, TFTP progress bar is increased for each received UDP frame, which can lead into long time being spent for sending From fa0f9e83a0654360506321e38c6d92888cb6f7ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 19 Dec 2024 11:52:46 +0100 Subject: [PATCH 3/3] net: rswitch: Add missing cache invalidate of TX descriptor TFTP transfers of large files, for example 128 MiB, can sporadically get stuck and the transfer slows down considerably. This happens because the TX DMA descriptor in DRAM becomes out of sync with the view of the TX DMA descriptor content from the CPU side, which is viewed through the CPU caches. In order to guarantee these two views are consistent, the cache over TX DMA descriptor that has possibly been written by the rswitch hardware must first be invalidated, only then can the descriptor be cleared and updated by the CPU, and finally the cache over that area must be flushed back into DRAM to make sure the rswitch hardware has consistent view of the updated descriptor content. The very first invalidation operation was missing, which led to sporadic corruption of the TX DMA descriptor. Fix it, add the missing invalidation operation. Reported-by: Enric Balletbo i Serra Signed-off-by: Marek Vasut Tested-by: Enric Balletbo i Serra --- drivers/net/rswitch.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6..97b5d1b75c1 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -837,6 +837,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) /* Update TX descriptor */ rswitch_flush_dcache((uintptr_t)packet, len); + rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len;