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rockchip: rk3328-orangepi-r1-plus: Update defconfig

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Update defconfig for rk3328-orangepi-r1-plus boards with new defaults.

Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.

Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.

Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.

Add DM_ETH_PHY=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove &gmac2io to
support reset of onboard ethernet PHYs.

Add PHY_ROCKCHIP_INNO_USB2=y option to support the onboard USB PHY.

Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.

Also add missing device tree files to MAINTAINERS file.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Tianling Shen <cnsztl@gmail.com>
This commit is contained in:
Jonas Karlman
2024-02-07 00:02:36 +00:00
parent 712eebd17c
commit a50774b582
6 changed files with 24 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
View File

@@ -28,12 +28,6 @@
bootph-pre-ram;
};
&gmac2io {
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
};
&spi0 {
spi_flash: spiflash@0 {
bootph-all;

6
arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
View File

@@ -28,12 +28,6 @@
bootph-pre-ram;
};
&gmac2io {
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
};
&spi0 {
spi_flash: spiflash@0 {
bootph-all;

2
board/rockchip/evb_rk3328/MAINTAINERS
View File

@@ -32,12 +32,14 @@ ORANGEPI-R1-PLUS-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/orangepi-r1-plus-rk3328_defconfig
F: arch/arm/dts/rk3328-orangepi-r1-plus.dts
F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
ORANGEPI-R1-PLUS-LTS-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/orangepi-r1-plus-lts-rk3328_defconfig
F: arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
ROC-RK3328-CC

12
configs/orangepi-r1-plus-lts-rk3328_defconfig
View File

@@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
@@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -57,8 +58,8 @@ CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -72,11 +73,16 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PHY_MOTORCOMM=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -91,6 +97,8 @@ CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

12
configs/orangepi-r1-plus-rk3328_defconfig
View File

@@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
@@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -57,8 +58,8 @@ CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -72,11 +73,16 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PHY_MOTORCOMM=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -91,6 +97,8 @@ CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

2
doc/board/rockchip/rockchip.rst
View File

@@ -66,6 +66,8 @@ List of mainline supported Rockchip boards:
- FriendlyElec NanoPi R2S (nanopi-r2s-rk3328)
- Pine64 Rock64 (rock64-rk3328)
- Radxa ROCK Pi E (rock-pi-e-rk3328)
- Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328)
- Xunlong Orange Pi R1 Plus LTS (orangepi-r1-plus-lts-rk3328)
* rk3368
- GeekBox (geekbox)
- PX5 EVB (evb-px5)