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Merge tag 'mmc-2021-7-30' of https://source.denx.de/u-boot/custodians/u-boot-mmc

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pl180_mmci update and cleanup
fix rpmb routing memory alignment
This commit is contained in:
Tom Rini
2021-08-02 08:53:58 -04:00
parent 72ffb41a87 d890f23406
commit 99bb5f248a
3 changed files with 38 additions and 29 deletions
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48
drivers/mmc/arm_pl180_mmci.c
View File

@@ -424,7 +424,6 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
struct pl180_mmc_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &pdata->cfg;
struct clk clk;
u32 bus_width;
u32 periphid;
int ret;
@@ -444,37 +443,35 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
SDI_CLKCR_HWFC_EN;
host->clock_in = clk_get_rate(&clk);
cfg->name = dev->name;
cfg->voltages = VOLTAGE_WINDOW_SD;
cfg->host_caps = 0;
cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
cfg->f_max = MMC_CLOCK_MAX;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
periphid = dev_read_u32_default(dev, "arm,primecell-periphid", 0);
switch (periphid) {
case STM32_MMCI_ID: /* stm32 variant */
host->version2 = false;
break;
case UX500V2_MMCI_ID:
host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | SDI_CLKCR_CLKEN |
SDI_CLKCR_HWFC_EN;
cfg->voltages = VOLTAGE_WINDOW_MMC;
cfg->f_min = host->clock_in / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
host->version2 = true;
break;
default:
host->version2 = true;
}
cfg->name = dev->name;
cfg->voltages = VOLTAGE_WINDOW_SD;
cfg->host_caps = 0;
cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
cfg->f_max = dev_read_u32_default(dev, "max-frequency", MMC_CLOCK_MAX);
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
bus_width = dev_read_u32_default(dev, "bus-width", 1);
switch (bus_width) {
case 8:
cfg->host_caps |= MMC_MODE_8BIT;
/* Hosts capable of 8-bit transfers can also do 4 bits */
case 4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
default:
dev_err(dev, "Invalid bus-width value %u\n", bus_width);
}
ret = mmc_of_parse(dev, cfg);
if (ret)
return ret;
arm_pl180_mmc_init(host);
mmc->priv = host;
@@ -526,20 +523,17 @@ static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = {
static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
{
struct pl180_mmc_host *host = dev_get_priv(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
host->base = dev_read_addr_ptr(dev);
if (!host->base)
return -EINVAL;
host->base = (void *)addr;
return 0;
}
static const struct udevice_id arm_pl180_mmc_match[] = {
{ .compatible = "arm,pl180" },
{ .compatible = "arm,primecell" },
{ .compatible = "arm,pl18x" },
{ /* sentinel */ }
};

1
drivers/mmc/arm_pl180_mmci.h
View File

@@ -142,6 +142,7 @@
#define SDI_FIFO_BURST_SIZE 8
#define STM32_MMCI_ID 0x00880180
#define UX500V2_MMCI_ID 0x10480180
struct sdi_registers {
u32 power; /* 0x00*/

18
drivers/mmc/rpmb.c
View File

@@ -480,10 +480,24 @@ int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
* and possibly just delay an eventual error which will be harder
* to track down.
*/
void *rpmb_data = NULL;
int ret;
if (reqlen % sizeof(struct s_rpmb) || rsplen % sizeof(struct s_rpmb))
return -EINVAL;
return rpmb_route_frames(mmc, req, reqlen / sizeof(struct s_rpmb),
rsp, rsplen / sizeof(struct s_rpmb));
if (!IS_ALIGNED((uintptr_t)req, ARCH_DMA_MINALIGN)) {
/* Memory alignment is required by MMC driver */
rpmb_data = malloc(reqlen);
if (!rpmb_data)
return -ENOMEM;
memcpy(rpmb_data, req, reqlen);
req = rpmb_data;
}
ret = rpmb_route_frames(mmc, req, reqlen / sizeof(struct s_rpmb),
rsp, rsplen / sizeof(struct s_rpmb));
free(rpmb_data);
return ret;
}