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Merge branch 'u-boot-nand-20241126' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/23584

Remove device specific nand driver files as they are now replaced by a
common driver bcmbca_nand.c

Make use of OF_UPSTREAM which uses Linux dts.

Implement a minimal set of defconfig options to enable basic NAND
functionality. Tested on:
47622
63146
63158
63178
6813

Set parameter_page_big_endian to zero for bcmbca.

Update log level messages so that more critical messages can be logged
to console and help the troubleshooting with field devices.
This commit is contained in:
Tom Rini
2024-11-27 07:33:06 -06:00
parent 3881c6b903 5b70f26fed
commit 931122add7
51 changed files with 132 additions and 2782 deletions
Download Patch File Download Diff File Expand all files Collapse all files

126
arch/arm/dts/bcm47622.dtsi
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@@ -1,126 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm47622", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>, <&CA7_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
cpu_off = <1>;
cpu_on = <2>;
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x818000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

128
arch/arm/dts/bcm4912.dtsi
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@@ -1,128 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm4912", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

110
arch/arm/dts/bcm63146.dtsi
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@@ -1,110 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm63146", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

278
arch/arm/dts/bcm63158.dtsi
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@@ -1,278 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm63158", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks {
bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm63158",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

120
arch/arm/dts/bcm63178.dtsi
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@@ -1,120 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm63178", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

130
arch/arm/dts/bcm6756.dtsi
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@@ -1,130 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6756", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>, <&CA7_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

128
arch/arm/dts/bcm6813.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6813", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

257
arch/arm/dts/bcm6855.dtsi
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@@ -1,257 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6855", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
};
clocks: clocks {
bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm6753",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
leds: led-controller@3000 {
compatible = "brcm,bcm6753-leds";
reg = <0x3000 0x3480>;
status = "disabled";
};
};
};

253
arch/arm/dts/bcm6856.dtsi
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@@ -1,253 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6856", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>;
};
clocks: clocks {
bootph-all;
periph_clk:periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>, /* GICD */
<0x2000 0x2000>, /* GICC */
<0x4000 0x2000>, /* GICH */
<0x6000 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm68360",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

272
arch/arm/dts/bcm6858.dtsi
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@@ -1,272 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6858", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks {
bootph-all;
periph_clk: periph_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>, /* GICD */
<0x2000 0x2000>, /* GICC */
<0x4000 0x2000>, /* GICH */
<0x6000 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
wdt1: watchdog@2780 {
compatible = "brcm,bcm6345-wdt";
reg = <0x2780 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@27c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x27c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm6858",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

111
arch/arm/dts/bcm6878.dtsi
View File

@@ -1,111 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6878", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

30
arch/arm/dts/bcm947622.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm47622.dtsi"
/ {
model = "Broadcom BCM947622 Reference Board";
compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm94912.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm4912.dtsi"
/ {
model = "Broadcom BCM94912 Reference Board";
compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963146.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63146.dtsi"
/ {
model = "Broadcom BCM963146 Reference Board";
compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963158.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63158.dtsi"
/ {
model = "Broadcom BCM963158 Reference Board";
compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963178.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63178.dtsi"
/ {
model = "Broadcom BCM963178 Reference Board";
compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96756.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6756.dtsi"
/ {
model = "Broadcom BCM96756 Reference Board";
compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96813.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6813.dtsi"
/ {
model = "Broadcom BCM96813 Reference Board";
compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96855.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6855.dtsi"
/ {
model = "Broadcom BCM96855 Reference Board";
compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96856.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6856.dtsi"
/ {
model = "Broadcom BCM96856 Reference Board";
compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96858.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6858.dtsi"
/ {
model = "Broadcom BCM96858 Reference Board";
compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96878.dts
View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6878.dtsi"
/ {
model = "Broadcom BCM96878 Reference Board";
compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

1
arch/arm/mach-bcmbca/bcm47622/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM47622
config TARGET_BCM947622
bool "Broadcom 47622 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm47622"

1
arch/arm/mach-bcmbca/bcm4912/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM4912
config TARGET_BCM94912
bool "Broadcom 4912 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm4912"

1
arch/arm/mach-bcmbca/bcm63146/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM63146
config TARGET_BCM963146
bool "Broadcom 63146 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63146"

1
arch/arm/mach-bcmbca/bcm63158/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM63158
config TARGET_BCM963158
bool "Broadcom 63158 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63158"

1
arch/arm/mach-bcmbca/bcm63178/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM63178
config TARGET_BCM963178
bool "Broadcom 63178 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63178"

1
arch/arm/mach-bcmbca/bcm6756/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM6756
config TARGET_BCM96756
bool "Broadcom 6756 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6756"

1
arch/arm/mach-bcmbca/bcm6813/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM6813
config TARGET_BCM96813
bool "Broadcom 6813 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6813"

1
arch/arm/mach-bcmbca/bcm6855/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM6855
config TARGET_BCM96855
bool "Broadcom 6855 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6855"

1
arch/arm/mach-bcmbca/bcm6856/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM6856
config TARGET_BCM96856
bool "Broadcom 6856 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6856"

1
arch/arm/mach-bcmbca/bcm6858/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM6858
config TARGET_BCM96858
bool "Broadcom 6858 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6858"

1
arch/arm/mach-bcmbca/bcm6878/Kconfig
View File

@@ -8,6 +8,7 @@ if BCM6878
config TARGET_BCM96878
bool "Broadcom 6878 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6878"

11
configs/bcm947622_defconfig
View File

@@ -8,7 +8,7 @@ CONFIG_TARGET_BCM947622=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm947622"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm947622"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM47622"
@@ -16,6 +16,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm94912_defconfig
View File

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM94912=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm94912"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM4912"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm963146_defconfig
View File

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963146=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963146"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63146"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm963158_defconfig
View File

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963158=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963158"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63158"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm963178_defconfig
View File

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM963178=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963178"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963178"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63178"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm96756_defconfig
View File

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96756=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96756"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96756"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6756"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm96813_defconfig
View File

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96813=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96813"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96813"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6813"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm96855_defconfig
View File

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96855=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96855"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6855"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm96856_defconfig
View File

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96856=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96856"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96856"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6856"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm96858_defconfig
View File

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96858=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96858"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96858"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6858"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

11
configs/bcm96878_defconfig
View File

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96878=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96878"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96878"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6878"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

24
drivers/mtd/nand/raw/Kconfig
View File

@@ -133,36 +133,12 @@ config NAND_BRCMNAND_6368
help
Enable support for broadcom nand driver on bcm6368.
config NAND_BRCMNAND_6753
bool "Support Broadcom NAND controller on bcm6753"
depends on NAND_BRCMNAND && BCM6855
help
Enable support for broadcom nand driver on bcm6753.
config NAND_BRCMNAND_68360
bool "Support Broadcom NAND controller on bcm68360"
depends on NAND_BRCMNAND && BCM6856
help
Enable support for broadcom nand driver on bcm68360.
config NAND_BRCMNAND_6838
bool "Support Broadcom NAND controller on bcm6838"
depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
help
Enable support for broadcom nand driver on bcm6838.
config NAND_BRCMNAND_6858
bool "Support Broadcom NAND controller on bcm6858"
depends on NAND_BRCMNAND && BCM6858
help
Enable support for broadcom nand driver on bcm6858.
config NAND_BRCMNAND_63158
bool "Support Broadcom NAND controller on bcm63158"
depends on NAND_BRCMNAND && BCM63158
help
Enable support for broadcom nand driver on bcm63158.
config NAND_BRCMNAND_IPROC
bool "Support Broadcom NAND controller on the iproc family"
depends on NAND_BRCMNAND

4
drivers/mtd/nand/raw/brcmnand/Makefile
View File

@@ -1,11 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o
obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o
obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o
obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o
obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o
obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o

125
drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c
View File

@@ -1,125 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
#include <memalign.h>
#include <nand.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
#include <linux/printk.h>
#include "brcmnand.h"
struct bcm63158_nand_soc {
struct brcmnand_soc soc;
void __iomem *base;
};
#define BCM63158_NAND_INT 0x00
#define BCM63158_NAND_STATUS_SHIFT 0
#define BCM63158_NAND_STATUS_MASK (0xfff << BCM63158_NAND_STATUS_SHIFT)
#define BCM63158_NAND_INT_EN 0x04
#define BCM63158_NAND_ENABLE_SHIFT 0
#define BCM63158_NAND_ENABLE_MASK (0xffff << BCM63158_NAND_ENABLE_SHIFT)
enum {
BCM63158_NP_READ = BIT(0),
BCM63158_BLOCK_ERASE = BIT(1),
BCM63158_COPY_BACK = BIT(2),
BCM63158_PAGE_PGM = BIT(3),
BCM63158_CTRL_READY = BIT(4),
BCM63158_DEV_RBPIN = BIT(5),
BCM63158_ECC_ERR_UNC = BIT(6),
BCM63158_ECC_ERR_CORR = BIT(7),
};
static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc)
{
struct bcm63158_nand_soc *priv =
container_of(soc, struct bcm63158_nand_soc, soc);
void __iomem *mmio = priv->base + BCM63158_NAND_INT;
u32 val = brcmnand_readl(mmio);
if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) {
/* Ack interrupt */
val &= ~BCM63158_NAND_STATUS_MASK;
val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT;
brcmnand_writel(val, mmio);
return true;
}
return false;
}
static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en)
{
struct bcm63158_nand_soc *priv =
container_of(soc, struct bcm63158_nand_soc, soc);
void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN;
u32 val = brcmnand_readl(mmio);
/* Don't ack any interrupts */
val &= ~BCM63158_NAND_STATUS_MASK;
if (en)
val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT;
else
val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT);
brcmnand_writel(val, mmio);
}
static int bcm63158_nand_probe(struct udevice *dev)
{
struct udevice *pdev = dev;
struct bcm63158_nand_soc *priv = dev_get_priv(dev);
struct brcmnand_soc *soc;
struct resource res;
soc = &priv->soc;
dev_read_resource_byname(pdev, "nand-int-base", &res);
priv->base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
soc->ctlrdy_ack = bcm63158_nand_intc_ack;
soc->ctlrdy_set_enabled = bcm63158_nand_intc_set;
/* Disable and ack all interrupts */
brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN);
brcmnand_writel(0, priv->base + BCM63158_NAND_INT);
return brcmnand_probe(pdev, soc);
}
static const struct udevice_id bcm63158_nand_dt_ids[] = {
{
.compatible = "brcm,nand-bcm63158",
},
{ /* sentinel */ }
};
U_BOOT_DRIVER(bcm63158_nand) = {
.name = "bcm63158-nand",
.id = UCLASS_MTD,
.of_match = bcm63158_nand_dt_ids,
.probe = bcm63158_nand_probe,
.priv_auto = sizeof(struct bcm63158_nand_soc),
};
void board_nand_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MTD,
DM_DRIVER_GET(bcm63158_nand), &dev);
if (ret && ret != -ENODEV)
pr_err("Failed to initialize %s. (error %d)\n", dev->name,
ret);
}

123
drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c
View File

@@ -1,123 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
#include <memalign.h>
#include <nand.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
#include "brcmnand.h"
struct bcm6753_nand_soc {
struct brcmnand_soc soc;
void __iomem *base;
};
#define BCM6753_NAND_INT 0x00
#define BCM6753_NAND_STATUS_SHIFT 0
#define BCM6753_NAND_STATUS_MASK (0xfff << BCM6753_NAND_STATUS_SHIFT)
#define BCM6753_NAND_INT_EN 0x04
#define BCM6753_NAND_ENABLE_SHIFT 0
#define BCM6753_NAND_ENABLE_MASK (0xffff << BCM6753_NAND_ENABLE_SHIFT)
enum {
BCM6753_NP_READ = BIT(0),
BCM6753_BLOCK_ERASE = BIT(1),
BCM6753_COPY_BACK = BIT(2),
BCM6753_PAGE_PGM = BIT(3),
BCM6753_CTRL_READY = BIT(4),
BCM6753_DEV_RBPIN = BIT(5),
BCM6753_ECC_ERR_UNC = BIT(6),
BCM6753_ECC_ERR_CORR = BIT(7),
};
static bool bcm6753_nand_intc_ack(struct brcmnand_soc *soc)
{
struct bcm6753_nand_soc *priv =
container_of(soc, struct bcm6753_nand_soc, soc);
void __iomem *mmio = priv->base + BCM6753_NAND_INT;
u32 val = brcmnand_readl(mmio);
if (val & (BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT)) {
/* Ack interrupt */
val &= ~BCM6753_NAND_STATUS_MASK;
val |= BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT;
brcmnand_writel(val, mmio);
return true;
}
return false;
}
static void bcm6753_nand_intc_set(struct brcmnand_soc *soc, bool en)
{
struct bcm6753_nand_soc *priv =
container_of(soc, struct bcm6753_nand_soc, soc);
void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN;
u32 val = brcmnand_readl(mmio);
/* Don't ack any interrupts */
val &= ~BCM6753_NAND_STATUS_MASK;
if (en)
val |= BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT;
else
val &= ~(BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT);
brcmnand_writel(val, mmio);
}
static int bcm6753_nand_probe(struct udevice *dev)
{
struct udevice *pdev = dev;
struct bcm6753_nand_soc *priv = dev_get_priv(dev);
struct brcmnand_soc *soc;
struct resource res;
soc = &priv->soc;
dev_read_resource_byname(pdev, "nand-int-base", &res);
priv->base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
soc->ctlrdy_ack = bcm6753_nand_intc_ack;
soc->ctlrdy_set_enabled = bcm6753_nand_intc_set;
/* Disable and ack all interrupts */
brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN);
brcmnand_writel(0, priv->base + BCM6753_NAND_INT);
return brcmnand_probe(pdev, soc);
}
static const struct udevice_id bcm6753_nand_dt_ids[] = {
{
.compatible = "brcm,nand-bcm6753",
},
{ /* sentinel */ }
};
U_BOOT_DRIVER(bcm6753_nand) = {
.name = "bcm6753-nand",
.id = UCLASS_MTD,
.of_match = bcm6753_nand_dt_ids,
.probe = bcm6753_nand_probe,
.priv_auto = sizeof(struct bcm6753_nand_soc),
};
void board_nand_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MTD,
DM_DRIVER_GET(bcm6753_nand), &dev);
if (ret && ret != -ENODEV)
pr_err("Failed to initialize %s. (error %d)\n", dev->name,
ret);
}

124
drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c
View File

@@ -1,124 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
#include <memalign.h>
#include <nand.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
#include <linux/printk.h>
#include "brcmnand.h"
struct bcm68360_nand_soc {
struct brcmnand_soc soc;
void __iomem *base;
};
#define BCM68360_NAND_INT 0x00
#define BCM68360_NAND_STATUS_SHIFT 0
#define BCM68360_NAND_STATUS_MASK (0xfff << BCM68360_NAND_STATUS_SHIFT)
#define BCM68360_NAND_INT_EN 0x04
#define BCM68360_NAND_ENABLE_SHIFT 0
#define BCM68360_NAND_ENABLE_MASK (0xffff << BCM68360_NAND_ENABLE_SHIFT)
enum {
BCM68360_NP_READ = BIT(0),
BCM68360_BLOCK_ERASE = BIT(1),
BCM68360_COPY_BACK = BIT(2),
BCM68360_PAGE_PGM = BIT(3),
BCM68360_CTRL_READY = BIT(4),
BCM68360_DEV_RBPIN = BIT(5),
BCM68360_ECC_ERR_UNC = BIT(6),
BCM68360_ECC_ERR_CORR = BIT(7),
};
static bool bcm68360_nand_intc_ack(struct brcmnand_soc *soc)
{
struct bcm68360_nand_soc *priv =
container_of(soc, struct bcm68360_nand_soc, soc);
void __iomem *mmio = priv->base + BCM68360_NAND_INT;
u32 val = brcmnand_readl(mmio);
if (val & (BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT)) {
/* Ack interrupt */
val &= ~BCM68360_NAND_STATUS_MASK;
val |= BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT;
brcmnand_writel(val, mmio);
return true;
}
return false;
}
static void bcm68360_nand_intc_set(struct brcmnand_soc *soc, bool en)
{
struct bcm68360_nand_soc *priv =
container_of(soc, struct bcm68360_nand_soc, soc);
void __iomem *mmio = priv->base + BCM68360_NAND_INT_EN;
u32 val = brcmnand_readl(mmio);
/* Don't ack any interrupts */
val &= ~BCM68360_NAND_STATUS_MASK;
if (en)
val |= BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT;
else
val &= ~(BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT);
brcmnand_writel(val, mmio);
}
static int bcm68360_nand_probe(struct udevice *dev)
{
struct udevice *pdev = dev;
struct bcm68360_nand_soc *priv = dev_get_priv(dev);
struct brcmnand_soc *soc;
struct resource res;
soc = &priv->soc;
dev_read_resource_byname(pdev, "nand-int-base", &res);
priv->base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
soc->ctlrdy_ack = bcm68360_nand_intc_ack;
soc->ctlrdy_set_enabled = bcm68360_nand_intc_set;
/* Disable and ack all interrupts */
brcmnand_writel(0, priv->base + BCM68360_NAND_INT_EN);
brcmnand_writel(0, priv->base + BCM68360_NAND_INT);
return brcmnand_probe(pdev, soc);
}
static const struct udevice_id bcm68360_nand_dt_ids[] = {
{
.compatible = "brcm,nand-bcm68360",
},
{ /* sentinel */ }
};
U_BOOT_DRIVER(bcm68360_nand) = {
.name = "bcm68360-nand",
.id = UCLASS_MTD,
.of_match = bcm68360_nand_dt_ids,
.probe = bcm68360_nand_probe,
.priv_auto = sizeof(struct bcm68360_nand_soc),
};
void board_nand_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MTD,
DM_DRIVER_GET(bcm68360_nand), &dev);
if (ret && ret != -ENODEV)
pr_err("Failed to initialize %s. (error %d)\n", dev->name,
ret);
}

125
drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
View File

@@ -1,125 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
#include <memalign.h>
#include <nand.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <dm.h>
#include <linux/printk.h>
#include "brcmnand.h"
struct bcm6858_nand_soc {
struct brcmnand_soc soc;
void __iomem *base;
};
#define BCM6858_NAND_INT 0x00
#define BCM6858_NAND_STATUS_SHIFT 0
#define BCM6858_NAND_STATUS_MASK (0xfff << BCM6858_NAND_STATUS_SHIFT)
#define BCM6858_NAND_INT_EN 0x04
#define BCM6858_NAND_ENABLE_SHIFT 0
#define BCM6858_NAND_ENABLE_MASK (0xffff << BCM6858_NAND_ENABLE_SHIFT)
enum {
BCM6858_NP_READ = BIT(0),
BCM6858_BLOCK_ERASE = BIT(1),
BCM6858_COPY_BACK = BIT(2),
BCM6858_PAGE_PGM = BIT(3),
BCM6858_CTRL_READY = BIT(4),
BCM6858_DEV_RBPIN = BIT(5),
BCM6858_ECC_ERR_UNC = BIT(6),
BCM6858_ECC_ERR_CORR = BIT(7),
};
static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc)
{
struct bcm6858_nand_soc *priv =
container_of(soc, struct bcm6858_nand_soc, soc);
void __iomem *mmio = priv->base + BCM6858_NAND_INT;
u32 val = brcmnand_readl(mmio);
if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) {
/* Ack interrupt */
val &= ~BCM6858_NAND_STATUS_MASK;
val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT;
brcmnand_writel(val, mmio);
return true;
}
return false;
}
static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en)
{
struct bcm6858_nand_soc *priv =
container_of(soc, struct bcm6858_nand_soc, soc);
void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN;
u32 val = brcmnand_readl(mmio);
/* Don't ack any interrupts */
val &= ~BCM6858_NAND_STATUS_MASK;
if (en)
val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT;
else
val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT);
brcmnand_writel(val, mmio);
}
static int bcm6858_nand_probe(struct udevice *dev)
{
struct udevice *pdev = dev;
struct bcm6858_nand_soc *priv = dev_get_priv(dev);
struct brcmnand_soc *soc;
struct resource res;
soc = &priv->soc;
dev_read_resource_byname(pdev, "nand-int-base", &res);
priv->base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
soc->ctlrdy_ack = bcm6858_nand_intc_ack;
soc->ctlrdy_set_enabled = bcm6858_nand_intc_set;
/* Disable and ack all interrupts */
brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN);
brcmnand_writel(0, priv->base + BCM6858_NAND_INT);
return brcmnand_probe(pdev, soc);
}
static const struct udevice_id bcm6858_nand_dt_ids[] = {
{
.compatible = "brcm,nand-bcm6858",
},
{ /* sentinel */ }
};
U_BOOT_DRIVER(bcm6858_nand) = {
.name = "bcm6858-nand",
.id = UCLASS_MTD,
.of_match = bcm6858_nand_dt_ids,
.probe = bcm6858_nand_probe,
.priv_auto = sizeof(struct bcm6858_nand_soc),
};
void board_nand_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MTD,
DM_DRIVER_GET(bcm6858_nand), &dev);
if (ret && ret != -ENODEV)
pr_err("Failed to initialize %s. (error %d)\n", dev->name,
ret);
}

14
drivers/mtd/nand/raw/brcmnand/brcmnand.c
View File

@@ -1071,8 +1071,8 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
if ((val & mask) == expected_val)
return 0;
dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
expected_val, val & mask);
dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
expected_val, val & mask);
return -ETIMEDOUT;
}
@@ -2032,7 +2032,7 @@ try_dmaread:
return err;
}
dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n",
(unsigned long long)err_addr);
mtd->ecc_stats.failed++;
/* NAND layer expects zero on ECC errors */
@@ -2793,9 +2793,17 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
nand_hw_control_init(&ctrl->controller);
INIT_LIST_HEAD(&ctrl->host_list);
#ifdef CONFIG_NAND_BRCMNAND_BCMBCA
/*
* BCMBCA platform does not use non-linux parameter-page-big-endian dts property,
* param page data is little endian
*/
ctrl->parameter_page_big_endian = 0;
#else
/* Is parameter page in big endian ? */
ctrl->parameter_page_big_endian =
dev_read_u32_default(dev, "parameter-page-big-endian", 1);
#endif
/* NAND register range */
#ifndef __UBOOT__