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spl: ARM: Enable CPU caches

Browse Source 
http://u-boot.10912.n7.nabble.com/RFC-PATCH-0-3-spl-Add-D-cache-support-td274750.html

Signed-off-by: Ondrej Jirman <megous@megous.com>
This commit is contained in:
Ondrej Jirman
2020-01-14 03:56:32 +01:00
parent e71d79c8eb
commit 878c0cd889
2 changed files with 72 additions and 0 deletions
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29
arch/arm/lib/cache-cp15.c
View File

@@ -106,6 +106,25 @@ __weak void dram_bank_mmu_setup(int bank)
}
}
#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_SPL_MAX_SIZE) || \
defined(CONFIG_SPL_MAX_FOOTPRINT))
__weak void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size)
{
int i;
for (i = start >> MMU_SECTION_SHIFT;
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
i++)
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
set_section_dcache(i, DCACHE_WRITEALLOC);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
}
#endif
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
@@ -121,6 +140,16 @@ static inline void mmu_setup(void)
dram_bank_mmu_setup(i);
}
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SPL_MAX_SIZE)
sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
ALIGN(CONFIG_SPL_MAX_SIZE, MMU_SECTION_SIZE));
#elif defined(CONFIG_SPL_MAX_FOOTPRINT)
sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
ALIGN(CONFIG_SPL_MAX_FOOTPRINT, MMU_SECTION_SIZE));
#endif
#endif
#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
/* Set up 4 PTE entries pointing to our 4 1GB page tables */
for (i = 0; i < 4; i++) {

43
common/spl/spl.c
View File

@@ -9,6 +9,7 @@
#include <common.h>
#include <bloblist.h>
#include <binman_sym.h>
#include <cpu_func.h>
#include <dm.h>
#include <handoff.h>
#include <irq_func.h>
@@ -590,6 +591,35 @@ void board_init_f(ulong dummy)
}
#endif
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
defined(CONFIG_ARM)
int reserve_mmu(void)
{
phys_addr_t ram_top = 0;
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
#ifdef CONFIG_SYS_SDRAM_BASE
ram_top = CONFIG_SYS_SDRAM_BASE;
#endif
ram_top += get_effective_memsize();
gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
return 0;
}
__weak int dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
#endif
return 0;
}
#endif
void board_init_r(gd_t *dummy1, ulong dummy2)
{
u32 spl_boot_list[] = {
@@ -606,6 +636,13 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
spl_set_bd();
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
defined(CONFIG_ARM)
dram_init_banksize();
reserve_mmu();
enable_caches();
#endif
#if defined(CONFIG_SYS_SPL_MALLOC_START)
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);
@@ -615,6 +652,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
if (spl_init())
hang();
}
#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6)
/*
* timer_init() does not exist on PPC systems. The timer is initialized
@@ -681,6 +719,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
ret);
}
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
defined(CONFIG_ARM)
cleanup_before_linux();
#endif
#ifdef CONFIG_CPU_V7M
spl_image.entry_point |= 0x1;
#endif