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dma: ti: k3-udma: Move udma_probe() below all APIs
The udma_probe() function was placed above many important APIs related to bcdma, pktdma, which restricts these APIs to be accessed during probe. So, move udma_probe() below all of them. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
This commit is contained in:
Santhosh Kumar K
committed by
Tom Rini
Tom Rini
parent
fd74f38f95
commit
7f069cc9fa
@@ -1700,141 +1700,6 @@ static int setup_resources(struct udma_dev *ud)
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return ch_count;
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}
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static int udma_probe(struct udevice *dev)
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{
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struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct udma_dev *ud = dev_get_priv(dev);
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int i, ret;
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struct udevice *tmp;
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struct udevice *tisci_dev = NULL;
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struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
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ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
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ud->match_data = (void *)dev_get_driver_data(dev);
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ret = udma_get_mmrs(dev);
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if (ret)
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return ret;
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ud->psil_base = ud->match_data->psil_base;
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ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
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"ti,sci", &tisci_dev);
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if (ret) {
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debug("Failed to get TISCI phandle (%d)\n", ret);
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tisci_rm->tisci = NULL;
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return -EINVAL;
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}
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tisci_rm->tisci = (struct ti_sci_handle *)
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(ti_sci_get_handle_from_sysfw(tisci_dev));
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tisci_rm->tisci_dev_id = -1;
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ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
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if (ret) {
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dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
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return ret;
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}
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tisci_rm->tisci_navss_dev_id = -1;
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ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
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&tisci_rm->tisci_navss_dev_id);
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if (ret) {
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dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
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return ret;
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}
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tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
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tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
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if (ud->match_data->type == DMA_TYPE_UDMA) {
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ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
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"ti,ringacc", &tmp);
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ud->ringacc = dev_get_priv(tmp);
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} else {
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struct k3_ringacc_init_data ring_init_data;
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ring_init_data.tisci = ud->tisci_rm.tisci;
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ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
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if (ud->match_data->type == DMA_TYPE_BCDMA) {
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ring_init_data.num_rings = ud->bchan_cnt +
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ud->tchan_cnt +
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ud->rchan_cnt;
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} else {
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ring_init_data.num_rings = ud->rflow_cnt +
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ud->tflow_cnt;
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}
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ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
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}
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if (IS_ERR(ud->ringacc))
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return PTR_ERR(ud->ringacc);
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ud->dev = dev;
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ret = setup_resources(ud);
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if (ret < 0)
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return ret;
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ud->ch_count = ret;
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for (i = 0; i < ud->bchan_cnt; i++) {
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struct udma_bchan *bchan = &ud->bchans[i];
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bchan->id = i;
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bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
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}
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for (i = 0; i < ud->tchan_cnt; i++) {
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struct udma_tchan *tchan = &ud->tchans[i];
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tchan->id = i;
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tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
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tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
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}
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for (i = 0; i < ud->rchan_cnt; i++) {
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struct udma_rchan *rchan = &ud->rchans[i];
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rchan->id = i;
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rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
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rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
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}
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for (i = 0; i < ud->rflow_cnt; i++) {
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struct udma_rflow *rflow = &ud->rflows[i];
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rflow->id = i;
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rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
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}
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for (i = 0; i < ud->ch_count; i++) {
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struct udma_chan *uc = &ud->channels[i];
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uc->ud = ud;
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uc->id = i;
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uc->config.remote_thread_id = -1;
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uc->bchan = NULL;
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uc->tchan = NULL;
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uc->rchan = NULL;
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uc->config.mapped_channel_id = -1;
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uc->config.default_flow_id = -1;
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uc->config.dir = DMA_MEM_TO_MEM;
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sprintf(uc->name, "UDMA chan%d\n", i);
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if (!i)
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uc->in_use = true;
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}
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pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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dev->name,
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udma_read(ud->mmrs[MMR_GCFG], 0),
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udma_read(ud->mmrs[MMR_GCFG], 0x20),
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udma_read(ud->mmrs[MMR_GCFG], 0x24),
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udma_read(ud->mmrs[MMR_GCFG], 0x28),
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udma_read(ud->mmrs[MMR_GCFG], 0x2c));
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uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
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return 0;
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}
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static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem)
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{
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u64 addr = 0;
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@@ -2717,6 +2582,141 @@ static int udma_get_cfg(struct dma *dma, u32 id, void **data)
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return -EINVAL;
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}
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static int udma_probe(struct udevice *dev)
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{
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struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct udma_dev *ud = dev_get_priv(dev);
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int i, ret;
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struct udevice *tmp;
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struct udevice *tisci_dev = NULL;
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struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
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ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
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ud->match_data = (void *)dev_get_driver_data(dev);
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ret = udma_get_mmrs(dev);
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if (ret)
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return ret;
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ud->psil_base = ud->match_data->psil_base;
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ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
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"ti,sci", &tisci_dev);
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if (ret) {
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debug("Failed to get TISCI phandle (%d)\n", ret);
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tisci_rm->tisci = NULL;
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return -EINVAL;
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}
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tisci_rm->tisci = (struct ti_sci_handle *)
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(ti_sci_get_handle_from_sysfw(tisci_dev));
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tisci_rm->tisci_dev_id = -1;
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ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
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if (ret) {
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dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
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return ret;
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}
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tisci_rm->tisci_navss_dev_id = -1;
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ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
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&tisci_rm->tisci_navss_dev_id);
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if (ret) {
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dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
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return ret;
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}
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tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
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tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
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if (ud->match_data->type == DMA_TYPE_UDMA) {
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ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
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"ti,ringacc", &tmp);
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ud->ringacc = dev_get_priv(tmp);
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} else {
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struct k3_ringacc_init_data ring_init_data;
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ring_init_data.tisci = ud->tisci_rm.tisci;
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ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
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if (ud->match_data->type == DMA_TYPE_BCDMA) {
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ring_init_data.num_rings = ud->bchan_cnt +
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ud->tchan_cnt +
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ud->rchan_cnt;
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} else {
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ring_init_data.num_rings = ud->rflow_cnt +
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ud->tflow_cnt;
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}
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ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
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}
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if (IS_ERR(ud->ringacc))
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return PTR_ERR(ud->ringacc);
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ud->dev = dev;
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ret = setup_resources(ud);
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if (ret < 0)
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return ret;
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ud->ch_count = ret;
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for (i = 0; i < ud->bchan_cnt; i++) {
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struct udma_bchan *bchan = &ud->bchans[i];
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bchan->id = i;
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bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
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}
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for (i = 0; i < ud->tchan_cnt; i++) {
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struct udma_tchan *tchan = &ud->tchans[i];
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tchan->id = i;
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tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
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tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
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}
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for (i = 0; i < ud->rchan_cnt; i++) {
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struct udma_rchan *rchan = &ud->rchans[i];
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rchan->id = i;
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rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
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rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
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}
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for (i = 0; i < ud->rflow_cnt; i++) {
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struct udma_rflow *rflow = &ud->rflows[i];
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rflow->id = i;
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rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
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}
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for (i = 0; i < ud->ch_count; i++) {
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struct udma_chan *uc = &ud->channels[i];
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uc->ud = ud;
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uc->id = i;
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uc->config.remote_thread_id = -1;
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uc->bchan = NULL;
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uc->tchan = NULL;
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uc->rchan = NULL;
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uc->config.mapped_channel_id = -1;
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uc->config.default_flow_id = -1;
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uc->config.dir = DMA_MEM_TO_MEM;
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sprintf(uc->name, "UDMA chan%d\n", i);
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if (!i)
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uc->in_use = true;
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}
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pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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dev->name,
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udma_read(ud->mmrs[MMR_GCFG], 0),
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udma_read(ud->mmrs[MMR_GCFG], 0x20),
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udma_read(ud->mmrs[MMR_GCFG], 0x24),
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udma_read(ud->mmrs[MMR_GCFG], 0x28),
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udma_read(ud->mmrs[MMR_GCFG], 0x2c));
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uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
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return 0;
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}
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static const struct dma_ops udma_ops = {
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.transfer = udma_transfer,
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.of_xlate = udma_of_xlate,
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