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dm: pch: Add get_io_base op

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On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
2016-02-01 01:40:45 -08:00
parent ec2af6f82d
commit 79d4eb627c
2 changed files with 29 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/pch/pch-uclass.c
View File

@@ -44,6 +44,17 @@ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
return ops->get_gpio_base(dev, gbasep);
}
int pch_get_io_base(struct udevice *dev, u32 *iobasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*iobasep = 0;
if (!ops->get_io_base)
return -ENOSYS;
return ops->get_io_base(dev, iobasep);
}
static int pch_uclass_post_bind(struct udevice *bus)
{
/*

18
include/pch.h
View File

@@ -41,6 +41,15 @@ struct pch_ops {
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
*/
int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
/**
* get_io_base() - get the address of IO base
*
* @dev: PCH device to check
* @iobasep: Returns address of IO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no IO base)
*/
int (*get_io_base)(struct udevice *dev, u32 *iobasep);
};
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
@@ -73,4 +82,13 @@ int pch_set_spi_protect(struct udevice *dev, bool protect);
*/
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
/**
* pch_get_io_base() - get the address of IO base
*
* @dev: PCH device to check
* @iobasep: Returns address of IO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no IO base)
*/
int pch_get_io_base(struct udevice *dev, u32 *iobasep);
#endif