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mmc: zynq_sdhci: Fix timing macros for MMC High speed

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Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with
correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1656319965-12124-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Ashok Reddy Soma
2022-06-27 14:22:45 +05:30
committed by Michal Simek
parent 156cb2af92
commit 71f0773148
1 changed files with 2 additions and 2 deletions
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4
drivers/mmc/zynq_sdhci.c
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@@ -101,8 +101,8 @@ static const u8 mode2timing[] = {
[MMC_LEGACY] = MMC_TIMING_LEGACY,
[MMC_HS] = MMC_TIMING_MMC_HS,
[SD_HS] = MMC_TIMING_SD_HS,
[MMC_HS_52] = MMC_TIMING_UHS_SDR50,
[MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
[MMC_HS_52] = MMC_TIMING_MMC_HS,
[MMC_DDR_52] = MMC_TIMING_MMC_DDR52,
[UHS_SDR12] = MMC_TIMING_UHS_SDR12,
[UHS_SDR25] = MMC_TIMING_UHS_SDR25,
[UHS_SDR50] = MMC_TIMING_UHS_SDR50,