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video: rockchip: dw_mipi_dsi: Improve pixel clock calculations
Calculate burst mode overhead in one place for both internal and external PHY use case and exit if out of range, instead of ignoring the wrong value. Signed-off-by: Ondrej Jirman <megi@xff.cz>
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@@ -526,8 +526,6 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
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struct udevice *dev = device->dev;
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struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
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int bpp;
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unsigned long mpclk, tmp;
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unsigned int target_mbps = 1000;
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unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
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unsigned long best_freq = 0;
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unsigned long fvco_min, fvco_max, fin, fout;
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@@ -544,30 +542,28 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
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return bpp;
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}
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mpclk = DIV_ROUND_UP(timings->pixelclock.typ, 1000);
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if (mpclk) {
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/* take 1 / 0.8, since mbps must big than bandwidth of RGB */
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tmp = (mpclk * (bpp / lanes) * 10 / 8) / 1000;
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if (tmp < max_mbps)
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target_mbps = tmp;
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else
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dev_err(dsi->dsi_host,
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"DPHY clock frequency is out of range\n");
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fout = timings->pixelclock.typ / MSEC_PER_SEC * bpp / lanes;
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if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
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fout = fout * 12 / 10;
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fout *= MSEC_PER_SEC;
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if (fout > max_mbps * USEC_PER_SEC) {
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dev_err(dsi->dsi_host, "DPHY clock frequency is out of range\n");
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return -EINVAL;
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}
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/* for external phy only the mipi_dphy_config is necessary */
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if (generic_phy_valid(&dsi->phy)) {
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phy_mipi_dphy_get_default_config(timings->pixelclock.typ * 10 / 8,
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phy_mipi_dphy_get_default_config(fout / bpp * lanes,
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bpp, lanes,
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&dsi->phy_opts);
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dsi->lane_mbps = target_mbps;
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dsi->lane_mbps = DIV_ROUND_UP(fout, USEC_PER_SEC);
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*lane_mbps = dsi->lane_mbps;
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return 0;
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}
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fin = clk_get_rate(dsi->ref);
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fout = target_mbps * USEC_PER_SEC;
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/* constraint: 5Mhz <= Fref / N <= 40MHz */
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min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
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