Merge branch 'master' of git://git.denx.de/u-boot into master

* 'master' of git://git.denx.de/u-boot: (113 commits)
  doc: qemu: debug UART settings for QEMU ARM virt
  MAINTAINERS: add myself as reviewer for SquashFS
  MAINTAINERS: add myself as reviewer for SquashFS
  lib: fdt: Fix fdtdec_setup_mem..() conversion to livetree API
  include: phy: fix NULL pointer check in phy_write()
  MAINTAINERS: update clk entry git tree
  rockchip: make_fit_atf: ignore empty PT_LOAD segment
  rockchip: rv1108: enable board early init
  rockchip: rv1108: Enable grf as pre-reloc node
  rockchip: rv1108: use correct API for board callback
  Azure/GitLab/Travis: Add SH4 r2dplus machine with various PCI ethernet options
  mmc: xenon_sdhci: Add missing common host capabilities
  mmc: msm_sdhci: Use mmc_of_parse for setting host_caps
  efi_selftest: restore gd before do_reset()
  efi_loader: save global data pointer on RISC-V
  riscv: define function set_gd()
  efi_loader: efi_var_mem_notify_exit_boot_services
  rsa: crash in br_i32_decode() called from rsa_gen_key_prop()
  test: do no assume hush parser in validate_empty()
  Makefile: mrproper shall delete doc/output/
  ...

arch/arm/dts/armada-3720-db.dts

@@ -159,6 +159,6 @@
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
-	reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };

arch/arm/dts/armada-3720-espressobin.dts

@@ -67,18 +67,29 @@
 		device_type = "memory";
 		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
 	};
+
+	vcc_sd_reg0: regulator@0 {
+		compatible = "regulator-gpio";
+		regulator-name = "vcc_sd0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-type = "voltage";
+		states = <1800000 0x1
+			  3300000 0x0>;
+		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 &comphy {
 	max-lanes = <3>;
 	phy0 {
-		phy-type = <PHY_TYPE_PEX0>;
-		phy-speed = <PHY_SPEED_2_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};
 
 	phy1 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-		phy-speed = <PHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_2_5G>;
 	};
 
 	phy2 {
@@ -110,6 +121,15 @@
 	status = "okay";
 };
 
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio_pins>;
+	bus-width = <4>;
+	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
+	vqmmc-supply = <&vcc_sd_reg0>;
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -145,6 +165,6 @@
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
-	reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };

arch/arm/dts/armada-3720-turris-mox.dts

@@ -172,6 +172,6 @@
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
-	reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 	status = "disabled";
 };

arch/arm/dts/k3-am65-mcu.dtsi

@@ -135,7 +135,7 @@
 				<0x0 0x2a500000 0x0 0x40000>;
 			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 			ti,num-rings = <286>;
-			ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
+			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 			ti,dma-ring-reset-quirk;
 			ti,sci = <&dmsc>;
 			ti,sci-dev-id = <195>;
@@ -153,11 +153,11 @@
 			ti,sci-dev-id = <194>;
 			ti,ringacc = <&mcu_ringacc>;
 
-			ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
-						<0x2>; /* TX_CHAN */
-			ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
-						<0x4>; /* RX_CHAN */
-			ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
+			ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
+						<0xd>; /* TX_CHAN */
+			ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
+						<0xa>; /* RX_CHAN */
+			ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
 		};
 	};
 

arch/arm/dts/rv1108-u-boot.dtsi

@@ -4,3 +4,7 @@
  */
 
 #include "rockchip-u-boot.dtsi"
+
+&grf {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi

@@ -75,6 +75,8 @@
 	};
 	pins2 {
 		u-boot,dm-pre-reloc;
+		/delete-property/ bias-disable;
+		bias-pull-up;
 	};
 };
 

arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

@@ -132,11 +132,11 @@
 		u-boot,dm-pre-reloc;
 	};
 
-	/* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
+	/* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
 	pll4: st,pll@3 {
 		compatible = "st,stm32mp1-pll";
 		reg = <3>;
-		cfg = < 1 49 5 11 5 PQR(1,1,1) >;
+		cfg = < 3 98 5 7 5 PQR(1,1,1) >;
 		u-boot,dm-pre-reloc;
 	};
 };

arch/arm/mach-imx/spl.c

@@ -187,6 +187,12 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 
 	return 0;
 }
+
+#define SDPV_BCD_DEVICE 0x500
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	return SDPV_BCD_DEVICE;
+}
 #endif
 
 #if defined(CONFIG_SPL_MMC_SUPPORT)

arch/arm/mach-mediatek/Kconfig

@@ -47,10 +47,10 @@ config TARGET_MT8512
         select ARM64
 	select MT8512
         help
-          The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53.
+          The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53.
           including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
-          Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
-          chip and several DDR3 and DDR4 options.
+          IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital
+          and several LPDDR3 and LPDDR4 options.
 
 config TARGET_MT8516
 	bool "MediaTek MT8516 SoC"

arch/arm/mach-meson/board-common.c

@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <cpu_func.h>
+#include <fastboot.h>
 #include <init.h>
 #include <net.h>
 #include <asm/arch/boot.h>
@@ -153,8 +154,11 @@ int board_late_init(void)
 #if CONFIG_IS_ENABLED(FASTBOOT)
 static unsigned int reboot_reason = REBOOT_REASON_NORMAL;
 
-int fastboot_set_reboot_flag()
+int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
 {
+	if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
+		return -ENOTSUPP;
+
 	reboot_reason = REBOOT_REASON_BOOTLOADER;
 
 	printf("Using reboot reason: 0x%x\n", reboot_reason);

arch/arm/mach-rockchip/board.c

@@ -6,6 +6,7 @@
 #include <clk.h>
 #include <cpu_func.h>
 #include <dm.h>
+#include <fastboot.h>
 #include <init.h>
 #include <log.h>
 #include <ram.h>
@@ -152,8 +153,11 @@ int board_usb_init(int index, enum usb_init_type init)
 #endif /* CONFIG_USB_GADGET */
 
 #if CONFIG_IS_ENABLED(FASTBOOT)
-int fastboot_set_reboot_flag(void)
+int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
 {
+	if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
+		return -ENOTSUPP;
+
 	printf("Setting reboot to fastboot flag ...\n");
 	/* Set boot mode to fastboot */
 	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);

arch/arm/mach-rockchip/make_fit_atf.py

@@ -189,8 +189,9 @@ def unpack_elf(filename):
         p_type, p_flags, p_offset = struct.unpack_from('<LLQ', elf, offset)
         if p_type == 1: # PT_LOAD
             p_paddr, p_filesz = struct.unpack_from('<2Q', elf, offset + 0x18)
-            p_data = elf[p_offset:p_offset + p_filesz]
-            segments.append((index, e_entry, p_paddr, p_data))
+            if p_filesz > 0:
+                p_data = elf[p_offset:p_offset + p_filesz]
+                segments.append((index, e_entry, p_paddr, p_data))
     return segments
 
 def main():

arch/arm/mach-socfpga/include/mach/misc.h

@@ -39,6 +39,11 @@ void socfpga_init_security_policies(void);
 void socfpga_sdram_remap_zero(void);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+int is_fpga_config_ready(void);
+#endif
+
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
 void socfpga_get_managers_addr(void);

arch/arm/mach-socfpga/include/mach/system_manager_soc64.h

@@ -88,8 +88,12 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
 #define SYSMGR_ECC_OCRAM_EN	BIT(0)
 #define SYSMGR_ECC_OCRAM_SERR	BIT(3)
 #define SYSMGR_ECC_OCRAM_DERR	BIT(4)
-#define SYSMGR_FPGAINTF_USEFPGA	0x1
+#define SYSMGR_FPGACONFIG_FPGA_COMPLETE		BIT(0)
+#define SYSMGR_FPGACONFIG_EARLY_USERMODE	BIT(1)
+#define SYSMGR_FPGACONFIG_READY_MASK	(SYSMGR_FPGACONFIG_FPGA_COMPLETE | \
+					 SYSMGR_FPGACONFIG_EARLY_USERMODE)
 
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
 #define SYSMGR_FPGAINTF_NAND	BIT(4)
 #define SYSMGR_FPGAINTF_SDMMC	BIT(8)
 #define SYSMGR_FPGAINTF_SPIM0	BIT(16)

arch/arm/mach-socfpga/misc_s10.c

@@ -151,17 +151,19 @@ int arch_early_init_r(void)
 	return 0;
 }
 
+/* Return 1 if FPGA is ready otherwise return 0 */
+int is_fpga_config_ready(void)
+{
+	return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
+		SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
+}
+
 void do_bridge_reset(int enable, unsigned int mask)
 {
 	/* Check FPGA status before bridge enable */
-	if (enable) {
-		int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
-
-		if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
-			ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
-		if (ret)
-			return;
+	if (!is_fpga_config_ready()) {
+		puts("FPGA not ready. Bridge reset aborted!\n");
+		return;
 	}
 
 	socfpga_bridges_reset(enable);

arch/arm/mach-stm32mp/cpu.c

@@ -580,8 +580,8 @@ __weak int setup_mac_address(void)
 		return -EINVAL;
 	}
 	pr_debug("OTP MAC address = %pM\n", enetaddr);
-	ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
-	if (!ret)
+	ret = eth_env_set_enetaddr("ethaddr", enetaddr);
+	if (ret)
 		pr_err("Failed to set mac address %pM from OTP: %d\n",
 		       enetaddr, ret);
 #endif

arch/riscv/include/asm/global_data.h

@@ -39,4 +39,13 @@ struct arch_global_data {
 
 #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
 
+static inline void set_gd(volatile gd_t *gd_ptr)
+{
+#ifdef CONFIG_64BIT
+	asm volatile("ld gp, %0\n" : : "m"(gd_ptr));
+#else
+	asm volatile("lw gp, %0\n" : : "m"(gd_ptr));
+#endif
+}
+
 #endif /* __ASM_GBL_DATA_H */

arch/x86/Kconfig

@@ -203,6 +203,9 @@ config SPL_X86_32BIT_INIT
 	help
 	  This is enabled when 32-bit init is in SPL
 
+config USE_EARLY_BOARD_INIT
+	bool
+
 config RESET_SEG_START
 	hex
 	depends on X86_RESET_VECTOR

arch/x86/cpu/start.S

@@ -88,6 +88,7 @@ _start:
 	/* Clear the interrupt vectors */
 	lidt	blank_idt_ptr
 
+#ifdef CONFIG_USE_EARLY_BOARD_INIT
 	/*
 	 * Critical early platform init - generally not used, we prefer init
 	 * to happen later when we have a console, in case something goes
@@ -96,6 +97,8 @@ _start:
 	jmp	early_board_init
 .globl early_board_init_ret
 early_board_init_ret:
+#endif
+
 	post_code(POST_START)
 
 	/* Initialise Cache-As-RAM */

arch/x86/include/asm/acpi_nhlt.h

@@ -137,14 +137,6 @@ int nhlt_endpoint_add_formats(struct nhlt_endpoint *endpoint,
  */
 void nhlt_next_instance(struct nhlt *nhlt, int link_type);
 
-/*
- * Serialize NHLT object to ACPI table. Take in the beginning address of where
- * the table will reside and return the address of the next ACPI table. On
- * error 0 will be returned. The NHLT object is no longer valid after this
- * function is called.
- */
-uintptr_t nhlt_serialise(struct nhlt *nhlt, uintptr_t acpi_addr);
-
 /*
  * Serialize NHLT object to ACPI table. Take in the beginning address of where
  * the table will reside oem_id and oem_table_id and return the address of the