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Merge branch 'master' of git://git.denx.de/u-boot into master

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* 'master' of git://git.denx.de/u-boot: (49 commits)
  scripts/setlocalversion: sync with linux 5.8
  image: don't exceed gd->ram_top in bootm_size
  cmd: mem: Remove already removed CONFIG_SYS_MEMTEST_SCRATCH
  lib/rsa: correct check after allocation in fdt_add_bignum()
  test: undefined reference to 'sscanf'
  checkpatch.pl: Make fdt / initrd relocation disabling an error
  env: Kconfig: Add missing dependency for ENV_IS_IN_EXT4
  arc: Kconfig: Add missing DM dependency
  cmd: Kconfig: Change dependency for CMD_ADC
  pci: kconfig: Setup proper dependency for PCIE_ROCKCHIP
  drivers: usb: Fix config indentation
  Prepare v2020.10-rc3
  configs: Resync with savedefconfig
  x86: qemu-x86_defconfig: Increase CONFIG_SYS_MALLOC_F_LEN
  imx8m: config: convert to bootm_size
  ARM: imx6q_logic: Fix broken booting by moving fdt_addr_r address
  pico-imx6: Remove unneeded CONFIG_DM_MDIO
  arm: mx6: Make all i.MX6 SoCs user-selectable
  arm: octeontx2: Add support for OcteonTX2 SoC platforms
  arm: octeontx: Add support for OcteonTX SoC platforms
  ...
This commit is contained in:
Ondrej Jirman
2020-08-30 10:18:26 +02:00
parent fc69ea9512 9f04a634ef
commit 254d171037
229 changed files with 35358 additions and 328 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@@ -3,7 +3,7 @@
VERSION = 2020
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*

1
arch/Kconfig
View File

@@ -12,6 +12,7 @@ config ARC
bool "ARC architecture"
select ARC_TIMER
select CLK
select DM
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select TIMER

24
arch/arm/Kconfig
View File

@@ -1737,6 +1737,24 @@ config ARCH_ROCKCHIP
imply TPL_SYSRESET
imply USB_FUNCTION_FASTBOOT
config ARCH_OCTEONTX
bool "Support OcteonTX SoCs"
select DM
select ARM64
select OF_CONTROL
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
config ARCH_OCTEONTX2
bool "Support OcteonTX2 SoCs"
select DM
select ARM64
select OF_CONTROL
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
@@ -1835,6 +1853,10 @@ source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-octeontx/Kconfig"
source "arch/arm/mach-octeontx2/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
@@ -1920,6 +1942,8 @@ source "board/bosch/guardian/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"

2
arch/arm/Makefile
View File

@@ -80,6 +80,8 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += u8500
machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ) += zynq

16
arch/arm/include/asm/arch-mx7/mx7-ddr.h
View File

@@ -136,11 +136,21 @@ struct ddr_phy {
u32 offset_wr_con0; /* 0x0030 */
u32 reserved5[0x07];
u32 cmd_sdll_con0; /* 0x0050 */
u32 reserved6[0x12];
u32 reserved6[0x06];
u32 cmd_lvl_con0; /* 0x006c */
u32 reserved7[0x02];
u32 cmd_lvl_con3; /* 0x0078 */
u32 cmd_deskew_con0; /* 0x007c */
u32 cmd_deskew_con1; /* 0x0080 */
u32 cmd_deskew_con2; /* 0x0084 */
u32 cmd_deskew_con3; /* 0x0088 */
u32 reserved8[0x02];
u32 cmd_deskew_con4; /* 0x0094 */
u32 reserved9;
u32 drvds_con0; /* 0x009c */
u32 reserved7[0x04];
u32 reserved10[0x04];
u32 mdll_con0; /* 0x00b0 */
u32 reserved8[0x03];
u32 reserved11[0x03];
u32 zq_con0; /* 0x00c0 */
};

123
arch/arm/include/asm/arch-octeontx/board.h Normal file
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@@ -0,0 +1,123 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <asm/arch/soc.h>
#define MAX_LMAC_PER_BGX 4
#define LMAC_CNT MAX_LMAC_PER_BGX
#if defined(CONFIG_TARGET_OCTEONTX_81XX)
/** Maximum number of BGX interfaces per CPU node */
#define MAX_BGX_PER_NODE 3
#define OCTEONTX_XCV /* RGMII Interface */
#elif defined(CONFIG_TARGET_OCTEONTX_83XX)
/** Maximum number of BGX interfaces per CPU node */
#define MAX_BGX_PER_NODE 4
#endif
/** Reg offsets */
#define RST_BOOT 0x87E006001600ULL
/** Structure definitions */
/**
* Register (RSL) rst_boot
*
* RST Boot Register This register is not accessible through ROM scripts;
* see SCR_WRITE32_S[ADDR].
*/
union rst_boot {
u64 u;
struct rst_boot_s {
u64 rboot_pin : 1;
u64 rboot : 1;
u64 reserved_2_32 : 31;
u64 pnr_mul : 6;
u64 reserved_39 : 1;
u64 c_mul : 7;
u64 reserved_47_52 : 6;
u64 gpio_ejtag : 1;
u64 mcp_jtagdis : 1;
u64 dis_scan : 1;
u64 dis_huk : 1;
u64 vrm_err : 1;
u64 jt_tstmode : 1;
u64 ckill_ppdis : 1;
u64 trusted_mode : 1;
u64 reserved_61_62 : 2;
u64 chipkill : 1;
} s;
struct rst_boot_cn81xx {
u64 rboot_pin : 1;
u64 rboot : 1;
u64 lboot : 10;
u64 lboot_ext23 : 6;
u64 lboot_ext45 : 6;
u64 lboot_jtg : 1;
u64 lboot_ckill : 1;
u64 reserved_26_29 : 4;
u64 lboot_oci : 3;
u64 pnr_mul : 6;
u64 reserved_39 : 1;
u64 c_mul : 7;
u64 reserved_47_54 : 8;
u64 dis_scan : 1;
u64 dis_huk : 1;
u64 vrm_err : 1;
u64 jt_tstmode : 1;
u64 ckill_ppdis : 1;
u64 trusted_mode : 1;
u64 ejtagdis : 1;
u64 jtcsrdis : 1;
u64 chipkill : 1;
} cn81xx;
struct rst_boot_cn83xx {
u64 rboot_pin : 1;
u64 rboot : 1;
u64 lboot : 10;
u64 lboot_ext23 : 6;
u64 lboot_ext45 : 6;
u64 lboot_jtg : 1;
u64 lboot_ckill : 1;
u64 lboot_pf_flr : 4;
u64 lboot_oci : 3;
u64 pnr_mul : 6;
u64 reserved_39 : 1;
u64 c_mul : 7;
u64 reserved_47_54 : 8;
u64 dis_scan : 1;
u64 dis_huk : 1;
u64 vrm_err : 1;
u64 jt_tstmode : 1;
u64 ckill_ppdis : 1;
u64 trusted_mode : 1;
u64 ejtagdis : 1;
u64 jtcsrdis : 1;
u64 chipkill : 1;
} cn83xx;
};
extern unsigned long fdt_base_addr;
/** Function definitions */
void mem_map_fill(void);
int octeontx_board_has_pmp(void);
const char *fdt_get_board_model(void);
const char *fdt_get_board_serial(void);
const char *fdt_get_board_revision(void);
void fdt_parse_phy_info(void);
void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth);
void bgx_set_board_info(int bgx_id, int *mdio_bus, int *phy_addr,
bool *autoneg_dis, bool *lmac_reg, bool *lmac_enable);
#endif /* __BOARD_H__ */

25
arch/arm/include/asm/arch-octeontx/clock.h Normal file
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@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __CLOCK_H__
#define __CLOCK_H__
/** System PLL reference clock */
#define PLL_REF_CLK 50000000 /* 50 MHz */
#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
/**
* Returns the I/O clock speed in Hz
*/
u64 octeontx_get_io_clock(void);
/**
* Returns the core clock speed in Hz
*/
u64 octeontx_get_core_clock(void);
#endif /* __CLOCK_H__ */

1193
arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h Normal file
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File diff suppressed because it is too large Load Diff

428
arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h Normal file
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@@ -0,0 +1,428 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __CSRS_XCV_H__
#define __CSRS_XCV_H__
/**
* @file
*
* Configuration and status register (CSR) address and type definitions for
* XCV.
*
* This file is auto generated. Do not edit.
*
*/
/**
* Enumeration xcv_bar_e
*
* XCV Base Address Register Enumeration Enumerates the base address
* registers.
*/
#define XCV_BAR_E_XCVX_PF_BAR0(a) (0x87e0db000000ll + 0ll * (a))
#define XCV_BAR_E_XCVX_PF_BAR0_SIZE 0x100000ull
#define XCV_BAR_E_XCVX_PF_BAR4(a) (0x87e0dbf00000ll + 0ll * (a))
#define XCV_BAR_E_XCVX_PF_BAR4_SIZE 0x100000ull
/**
* Enumeration xcv_int_vec_e
*
* XCV MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors.
*/
#define XCV_INT_VEC_E_INT (0)
/**
* Register (RSL) xcv#_batch_crd_ret
*
* XCV Batch Credit Return Register
*/
union xcvx_batch_crd_ret {
u64 u;
struct xcvx_batch_crd_ret_s {
u64 crd_ret : 1;
u64 reserved_1_63 : 63;
} s;
/* struct xcvx_batch_crd_ret_s cn; */
};
static inline u64 XCVX_BATCH_CRD_RET(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_BATCH_CRD_RET(u64 a)
{
return 0x100 + 0 * a;
}
/**
* Register (RSL) xcv#_comp_ctl
*
* XCV Compensation Controller Register This register controls
* programmable compensation.
*/
union xcvx_comp_ctl {
u64 u;
struct xcvx_comp_ctl_s {
u64 nctl_sat : 1;
u64 reserved_1_26 : 26;
u64 nctl_lock : 1;
u64 reserved_28 : 1;
u64 pctl_sat : 1;
u64 pctl_lock : 1;
u64 reserved_31 : 1;
u64 drv_nctl : 5;
u64 reserved_37_39 : 3;
u64 drv_pctl : 5;
u64 reserved_45_47 : 3;
u64 cmp_nctl : 5;
u64 reserved_53_55 : 3;
u64 cmp_pctl : 5;
u64 reserved_61_62 : 2;
u64 drv_byp : 1;
} s;
/* struct xcvx_comp_ctl_s cn; */
};
static inline u64 XCVX_COMP_CTL(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_COMP_CTL(u64 a)
{
return 0x20 + 0 * a;
}
/**
* Register (RSL) xcv#_ctl
*
* XCV Control Register This register contains the status control bits.
*/
union xcvx_ctl {
u64 u;
struct xcvx_ctl_s {
u64 speed : 2;
u64 lpbk_int : 1;
u64 lpbk_ext : 1;
u64 reserved_4_63 : 60;
} s;
/* struct xcvx_ctl_s cn; */
};
static inline u64 XCVX_CTL(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_CTL(u64 a)
{
return 0x30 + 0 * a;
}
/**
* Register (RSL) xcv#_dll_ctl
*
* XCV DLL Controller Register The RGMII timing specification requires
* that devices transmit clock and data synchronously. The specification
* requires external sources (namely the PC board trace routes) to
* introduce the appropriate 1.5 to 2.0 ns of delay. To eliminate the
* need for the PC board delays, the RGMII interface has optional on-
* board DLLs for both transmit and receive. For correct operation, at
* most one of the transmitter, board, or receiver involved in an RGMII
* link should introduce delay. By default/reset, the RGMII receivers
* delay the received clock, and the RGMII transmitters do not delay the
* transmitted clock. Whether this default works as-is with a given link
* partner depends on the behavior of the link partner and the PC board.
* These are the possible modes of RGMII receive operation: *
* XCV()_DLL_CTL[CLKRX_BYP] = 0 (reset value) - The RGMII receive
* interface introduces clock delay using its internal DLL. This mode is
* appropriate if neither the remote transmitter nor the PC board delays
* the clock. * XCV()_DLL_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The
* RGMII receive interface introduces no clock delay. This mode is
* appropriate if either the remote transmitter or the PC board delays
* the clock. These are the possible modes of RGMII transmit operation:
* * XCV()_DLL_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) - The
* RGMII transmit interface introduces no clock delay. This mode is
* appropriate is either the remote receiver or the PC board delays the
* clock. * XCV()_DLL_CTL[CLKTX_BYP] = 0 - The RGMII transmit interface
* introduces clock delay using its internal DLL. This mode is
* appropriate if neither the remote receiver nor the PC board delays the
* clock.
*/
union xcvx_dll_ctl {
u64 u;
struct xcvx_dll_ctl_s {
u64 refclk_sel : 2;
u64 reserved_2_7 : 6;
u64 clktx_set : 7;
u64 clktx_byp : 1;
u64 clkrx_set : 7;
u64 clkrx_byp : 1;
u64 clk_set : 7;
u64 lock : 1;
u64 reserved_32_63 : 32;
} s;
/* struct xcvx_dll_ctl_s cn; */
};
static inline u64 XCVX_DLL_CTL(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_DLL_CTL(u64 a)
{
return 0x10 + 0 * a;
}
/**
* Register (RSL) xcv#_eco
*
* INTERNAL: XCV ECO Register
*/
union xcvx_eco {
u64 u;
struct xcvx_eco_s {
u64 eco_rw : 16;
u64 reserved_16_63 : 48;
} s;
/* struct xcvx_eco_s cn; */
};
static inline u64 XCVX_ECO(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_ECO(u64 a)
{
return 0x200 + 0 * a;
}
/**
* Register (RSL) xcv#_inbnd_status
*
* XCV Inband Status Register This register contains RGMII inband status.
*/
union xcvx_inbnd_status {
u64 u;
struct xcvx_inbnd_status_s {
u64 link : 1;
u64 speed : 2;
u64 duplex : 1;
u64 reserved_4_63 : 60;
} s;
/* struct xcvx_inbnd_status_s cn; */
};
static inline u64 XCVX_INBND_STATUS(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_INBND_STATUS(u64 a)
{
return 0x80 + 0 * a;
}
/**
* Register (RSL) xcv#_int
*
* XCV Interrupt Register This register flags error for TX FIFO overflow,
* TX FIFO underflow and incomplete byte for 10/100 Mode. It also flags
* status change for link duplex, link speed and link up/down.
*/
union xcvx_int {
u64 u;
struct xcvx_int_s {
u64 link : 1;
u64 speed : 1;
u64 reserved_2 : 1;
u64 duplex : 1;
u64 incomp_byte : 1;
u64 tx_undflw : 1;
u64 tx_ovrflw : 1;
u64 reserved_7_63 : 57;
} s;
/* struct xcvx_int_s cn; */
};
static inline u64 XCVX_INT(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_INT(u64 a)
{
return 0x40 + 0 * a;
}
/**
* Register (RSL) xcv#_int_ena_w1c
*
* Loopback Error Interrupt Enable Clear Register This register clears
* interrupt enable bits.
*/
union xcvx_int_ena_w1c {
u64 u;
struct xcvx_int_ena_w1c_s {
u64 link : 1;
u64 speed : 1;
u64 reserved_2 : 1;
u64 duplex : 1;
u64 incomp_byte : 1;
u64 tx_undflw : 1;
u64 tx_ovrflw : 1;
u64 reserved_7_63 : 57;
} s;
/* struct xcvx_int_ena_w1c_s cn; */
};
static inline u64 XCVX_INT_ENA_W1C(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_INT_ENA_W1C(u64 a)
{
return 0x50 + 0 * a;
}
/**
* Register (RSL) xcv#_int_ena_w1s
*
* Loopback Error Interrupt Enable Set Register This register sets
* interrupt enable bits.
*/
union xcvx_int_ena_w1s {
u64 u;
struct xcvx_int_ena_w1s_s {
u64 link : 1;
u64 speed : 1;
u64 reserved_2 : 1;
u64 duplex : 1;
u64 incomp_byte : 1;
u64 tx_undflw : 1;
u64 tx_ovrflw : 1;
u64 reserved_7_63 : 57;
} s;
/* struct xcvx_int_ena_w1s_s cn; */
};
static inline u64 XCVX_INT_ENA_W1S(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_INT_ENA_W1S(u64 a)
{
return 0x58 + 0 * a;
}
/**
* Register (RSL) xcv#_int_w1s
*
* Loopback Error Interrupt Set Register This register sets interrupt
* bits.
*/
union xcvx_int_w1s {
u64 u;
struct xcvx_int_w1s_s {
u64 link : 1;
u64 speed : 1;
u64 reserved_2 : 1;
u64 duplex : 1;
u64 incomp_byte : 1;
u64 tx_undflw : 1;
u64 tx_ovrflw : 1;
u64 reserved_7_63 : 57;
} s;
/* struct xcvx_int_w1s_s cn; */
};
static inline u64 XCVX_INT_W1S(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_INT_W1S(u64 a)
{
return 0x48 + 0 * a;
}
/**
* Register (RSL) xcv#_msix_pba#
*
* XCV MSI-X Pending Bit Array Registers This register is the MSI-X PBA
* table; the bit number is indexed by the XCV_INT_VEC_E enumeration.
*/
union xcvx_msix_pbax {
u64 u;
struct xcvx_msix_pbax_s {
u64 pend : 64;
} s;
/* struct xcvx_msix_pbax_s cn; */
};
static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b)
{
return 0xf0000 + 0 * a + 8 * b;
}
/**
* Register (RSL) xcv#_msix_vec#_addr
*
* XCV MSI-X Vector-Table Address Register This register is the MSI-X
* vector table, indexed by the XCV_INT_VEC_E enumeration.
*/
union xcvx_msix_vecx_addr {
u64 u;
struct xcvx_msix_vecx_addr_s {
u64 secvec : 1;
u64 reserved_1 : 1;
u64 addr : 47;
u64 reserved_49_63 : 15;
} s;
/* struct xcvx_msix_vecx_addr_s cn; */
};
static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b)
{
return 0 + 0 * a + 0x10 * b;
}
/**
* Register (RSL) xcv#_msix_vec#_ctl
*
* XCV MSI-X Vector-Table Control and Data Register This register is the
* MSI-X vector table, indexed by the XCV_INT_VEC_E enumeration.
*/
union xcvx_msix_vecx_ctl {
u64 u;
struct xcvx_msix_vecx_ctl_s {
u64 data : 20;
u64 reserved_20_31 : 12;
u64 mask : 1;
u64 reserved_33_63 : 31;
} s;
/* struct xcvx_msix_vecx_ctl_s cn; */
};
static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b)
{
return 8 + 0 * a + 0x10 * b;
}
/**
* Register (RSL) xcv#_reset
*
* XCV Reset Registers This register controls reset.
*/
union xcvx_reset {
u64 u;
struct xcvx_reset_s {
u64 rx_dat_rst_n : 1;
u64 rx_pkt_rst_n : 1;
u64 tx_dat_rst_n : 1;
u64 tx_pkt_rst_n : 1;
u64 reserved_4_6 : 3;
u64 comp : 1;
u64 reserved_8_10 : 3;
u64 dllrst : 1;
u64 reserved_12_14 : 3;
u64 clkrst : 1;
u64 reserved_16_62 : 47;
u64 enable : 1;
} s;
/* struct xcvx_reset_s cn; */
};
static inline u64 XCVX_RESET(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 XCVX_RESET(u64 a)
{
return 0 + 0 * a;
}
#endif /* __CSRS_XCV_H__ */

6
arch/arm/include/asm/arch-octeontx/gpio.h Normal file
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@@ -0,0 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/

20
arch/arm/include/asm/arch-octeontx/smc.h Normal file
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@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __SMC_H__
#define __SMC_H__
/* OcteonTX Service Calls version numbers */
#define OCTEONTX_VERSION_MAJOR 0x1
#define OCTEONTX_VERSION_MINOR 0x0
/* x1 - node number */
#define OCTEONTX_DRAM_SIZE 0xc2000301
ssize_t smc_dram_size(unsigned int node);
#endif /* __SMC_H__ */

33
arch/arm/include/asm/arch-octeontx/soc.h Normal file
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@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __SOC_H__
#define __SOC_H__
/* Product PARTNUM */
#define CN81XX 0xA2
#define CN83XX 0xA3
#define CN96XX 0xB2
#define CN95XX 0xB3
#define otx_is_altpkg() read_alt_pkg()
#define otx_is_soc(soc) (read_partnum() == (soc))
#define otx_is_board(model) (!strcmp(read_board_name(), model))
#define otx_is_platform(platform) (read_platform() == (platform))
enum platform {
PLATFORM_HW = 0,
PLATFORM_EMULATOR = 1,
PLATFORM_ASIM = 3,
};
int read_platform(void);
u8 read_partnum(void);
const char *read_board_name(void);
bool read_alt_pkg(void);
#endif /* __SOC_H */

128
arch/arm/include/asm/arch-octeontx2/board.h Normal file
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@@ -0,0 +1,128 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <asm/arch/soc.h>
/** Reg offsets */
#define RST_BOOT 0x87E006001600ULL
#define CPC_BOOT_OWNERX(a) 0x86D000000160ULL + (8 * (a))
/** Structure definitions */
/**
* Register (NCB32b) cpc_boot_owner#
*
* CPC Boot Owner Registers These registers control an external arbiter
* for the boot device (SPI/eMMC) across multiple external devices. There
* is a register for each requester: _ \<0\> - SCP - reset on
* SCP reset _ \<1\> - MCP - reset on MCP reset _ \<2\> - AP
* Secure - reset on core reset _ \<3\> - AP Nonsecure - reset on core
* reset These register is only writable to the corresponding
* requestor(s) permitted with CPC_PERMIT.
*/
union cpc_boot_ownerx {
u32 u;
struct cpc_boot_ownerx_s {
u32 boot_req : 1;
u32 reserved_1_7 : 7;
u32 boot_wait : 1;
u32 reserved_9_31 : 23;
} s;
};
/**
* Register (RSL) rst_boot
*
* RST Boot Register This register is not accessible through ROM scripts;
* see SCR_WRITE32_S[ADDR].
*/
union rst_boot {
u64 u;
struct rst_boot_s {
u64 rboot_pin : 1;
u64 rboot : 1;
u64 reserved_2_32 : 31;
u64 pnr_mul : 6;
u64 reserved_39 : 1;
u64 c_mul : 7;
u64 reserved_47_52 : 6;
u64 gpio_ejtag : 1;
u64 mcp_jtagdis : 1;
u64 dis_scan : 1;
u64 dis_huk : 1;
u64 vrm_err : 1;
u64 jt_tstmode : 1;
u64 ckill_ppdis : 1;
u64 trusted_mode : 1;
u64 reserved_61_62 : 2;
u64 chipkill : 1;
} s;
struct rst_boot_cn96xx {
u64 rboot_pin : 1;
u64 rboot : 1;
u64 reserved_2_23 : 22;
u64 cpt_mul : 7;
u64 reserved_31_32 : 2;
u64 pnr_mul : 6;
u64 reserved_39 : 1;
u64 c_mul : 7;
u64 reserved_47_52 : 6;
u64 gpio_ejtag : 1;
u64 mcp_jtagdis : 1;
u64 dis_scan : 1;
u64 dis_huk : 1;
u64 vrm_err : 1;
u64 reserved_58_59 : 2;
u64 trusted_mode : 1;
u64 scp_jtagdis : 1;
u64 jtagdis : 1;
u64 chipkill : 1;
} cn96xx;
struct rst_boot_cnf95xx {
u64 rboot_pin : 1;
u64 rboot : 1;
u64 reserved_2_7 : 6;
u64 bphy_mul : 7;
u64 reserved_15 : 1;
u64 dsp_mul : 7;
u64 reserved_23 : 1;
u64 cpt_mul : 7;
u64 reserved_31_32 : 2;
u64 pnr_mul : 6;
u64 reserved_39 : 1;
u64 c_mul : 7;
u64 reserved_47_52 : 6;
u64 gpio_ejtag : 1;
u64 mcp_jtagdis : 1;
u64 dis_scan : 1;
u64 dis_huk : 1;
u64 vrm_err : 1;
u64 reserved_58_59 : 2;
u64 trusted_mode : 1;
u64 scp_jtagdis : 1;
u64 jtagdis : 1;
u64 chipkill : 1;
} cnf95xx;
};
extern unsigned long fdt_base_addr;
/** Function definitions */
void mem_map_fill(void);
int fdt_get_board_mac_cnt(void);
u64 fdt_get_board_mac_addr(void);
const char *fdt_get_board_model(void);
const char *fdt_get_board_serial(void);
const char *fdt_get_board_revision(void);
void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr);
void board_acquire_flash_arb(bool acquire);
void cgx_intf_shutdown(void);
#endif /* __BOARD_H__ */

24
arch/arm/include/asm/arch-octeontx2/clock.h Normal file
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@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __CLOCK_H__
/** System PLL reference clock */
#define PLL_REF_CLK 50000000 /* 50 MHz */
#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
/**
* Returns the I/O clock speed in Hz
*/
u64 octeontx_get_io_clock(void);
/**
* Returns the core clock speed in Hz
*/
u64 octeontx_get_core_clock(void);
#endif /* __CLOCK_H__ */

7851
arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h Normal file
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File diff suppressed because it is too large Load Diff

60
arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h Normal file
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@@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __CSRS_LMT_H__
#define __CSRS_LMT_H__
/**
* @file
*
* Configuration and status register (CSR) address and type definitions for
* LMT.
*
* This file is auto generated. Do not edit.
*
*/
/**
* Register (RVU_PFVF_BAR2) lmt_lf_lmtcancel
*
* RVU VF LMT Cancel Register
*/
union lmt_lf_lmtcancel {
u64 u;
struct lmt_lf_lmtcancel_s {
u64 data : 64;
} s;
/* struct lmt_lf_lmtcancel_s cn; */
};
static inline u64 LMT_LF_LMTCANCEL(void)
__attribute__ ((pure, always_inline));
static inline u64 LMT_LF_LMTCANCEL(void)
{
return 0x400;
}
/**
* Register (RVU_PFVF_BAR2) lmt_lf_lmtline#
*
* RVU VF LMT Line Registers
*/
union lmt_lf_lmtlinex {
u64 u;
struct lmt_lf_lmtlinex_s {
u64 data : 64;
} s;
/* struct lmt_lf_lmtlinex_s cn; */
};
static inline u64 LMT_LF_LMTLINEX(u64 a)
__attribute__ ((pure, always_inline));
static inline u64 LMT_LF_LMTLINEX(u64 a)
{
return 0 + 8 * a;
}
#endif /* __CSRS_LMT_H__ */

1193
arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h Normal file
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10404
arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h Normal file
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2294
arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h Normal file
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1629
arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h Normal file
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File diff suppressed because it is too large Load Diff

2276
arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h Normal file
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File diff suppressed because it is too large Load Diff

6
arch/arm/include/asm/arch-octeontx2/gpio.h Normal file
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@@ -0,0 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/

32
arch/arm/include/asm/arch-octeontx2/smc-id.h Normal file
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@@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __SMC_ID_H__
#define __SMC_ID_H__
/* SMC function IDs for general purpose queries */
#define OCTEONTX2_SVC_CALL_COUNT 0xc200ff00
#define OCTEONTX2_SVC_UID 0xc200ff01
#define OCTEONTX2_SVC_VERSION 0xc200ff03
/* OcteonTX Service Calls version numbers */
#define OCTEONTX2_VERSION_MAJOR 0x1
#define OCTEONTX2_VERSION_MINOR 0x0
/* x1 - node number */
#define OCTEONTX2_DRAM_SIZE 0xc2000301
#define OCTEONTX2_NODE_COUNT 0xc2000601
#define OCTEONTX2_DISABLE_RVU_LFS 0xc2000b01
#define OCTEONTX2_CONFIG_OOO 0xc2000b04
/* fail safe */
#define OCTEONTX2_FSAFE_PR_BOOT_SUCCESS 0xc2000b02
#endif /* __SMC_ID_H__ */

18
arch/arm/include/asm/arch-octeontx2/smc.h Normal file
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@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __SMC_H__
#define __SMC_H__
#include <asm/arch/smc-id.h>
ssize_t smc_configure_ooo(unsigned int val);
ssize_t smc_dram_size(unsigned int node);
ssize_t smc_disable_rvu_lfs(unsigned int node);
ssize_t smc_flsf_fw_booted(void);
#endif

33
arch/arm/include/asm/arch-octeontx2/soc.h Normal file
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@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2019 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#ifndef __SOC_H__
#define __SOC_H__
/* Product PARTNUM */
#define CN81XX 0xA2
#define CN83XX 0xA3
#define CN96XX 0xB2
#define CN95XX 0xB3
/* Register defines */
#define otx_is_soc(soc) (read_partnum() == (soc))
#define otx_is_board(model) (!strcmp(read_board_name(), model))
#define otx_is_platform(platform) (read_platform() == (platform))
enum platform_t {
PLATFORM_HW = 0,
PLATFORM_EMULATOR = 1,
PLATFORM_ASIM = 3,
};
int read_platform(void);
u8 read_partnum(void);
const char *read_board_name(void);
#endif /* __SOC_H */

16
arch/arm/include/asm/io.h
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@@ -180,16 +180,20 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
#define in_le32(a) in_arch(l,le32,a)
#define in_le16(a) in_arch(w,le16,a)
#define out_be64(a,v) out_arch(l,be64,a,v)
#define out_be32(a,v) out_arch(l,be32,a,v)
#define out_be16(a,v) out_arch(w,be16,a,v)
#define in_be64(a) in_arch(l,be64,a)
#define in_be32(a) in_arch(l,be32,a)
#define in_be16(a) in_arch(w,be16,a)
#define out_64(a,v) __raw_writeq(v,a)
#define out_32(a,v) __raw_writel(v,a)
#define out_16(a,v) __raw_writew(v,a)
#define out_8(a,v) __raw_writeb(v,a)
#define in_64(a) __raw_readq(a)
#define in_32(a) __raw_readl(a)
#define in_16(a) __raw_readw(a)
#define in_8(a) __raw_readb(a)
@@ -231,6 +235,18 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
#define clrbits_be64(addr, clear) clrbits(be64, addr, clear)
#define setbits_be64(addr, set) setbits(be64, addr, set)
#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
#define clrbits_le64(addr, clear) clrbits(le64, addr, clear)
#define setbits_le64(addr, set) setbits(le64, addr, set)
#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
#define clrbits_64(addr, clear) clrbits(64, addr, clear)
#define setbits_64(addr, set) setbits(64, addr, set)
#define clrsetbits_64(addr, clear, set) clrsetbits(64, addr, clear, set)
/*
* Now, pick up the machine-defined IO definitions
*/

2
arch/arm/include/asm/mach-imx/boot_mode.h
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@@ -7,6 +7,8 @@
#define _ASM_BOOT_MODE_H
#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
#define MAKE_CFGVAL_PRIMARY_BOOT 0xfffffff0
#define MAKE_CFGVAL_SECONDARY_BOOT 0xffffffff
enum boot_device {
WEIM_NOR_BOOT,

8
arch/arm/include/asm/mach-imx/sys_proto.h
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@@ -78,7 +78,8 @@ struct bd_info;
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#ifdef CONFIG_MX6
#define IMX6_SRC_GPR10_BMODE BIT(28)
#define IMX6_SRC_GPR10_BMODE BIT(28)
#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define IMX6_BMODE_MASK GENMASK(7, 0)
#define IMX6_BMODE_SHIFT 4
@@ -126,6 +127,11 @@ void gpr_init(void);
#endif /* CONFIG_MX6 */
#ifdef CONFIG_MX7
#define IMX7_SRC_GPR10_BMODE BIT(28)
#define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#endif
/* address translation table */
struct rproc_att {
u32 da; /* device address (From Cortex M4 view) */

2
arch/arm/mach-imx/Kconfig
View File

@@ -62,7 +62,7 @@ config CSF_SIZE
config CMD_BMODE
bool "Support the 'bmode' command"
default y
depends on ARCH_MX6 || ARCH_MX5
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
help
This enables the 'bmode' (bootmode) command for forcing
a boot from specific media.

12
arch/arm/mach-imx/cmd_bmode.c
View File

@@ -51,9 +51,19 @@ static int create_usage(char *dest)
if (dest)
memcpy(dest - 1, " [noreset]", 11); /* include trailing 0 */
size += 10;
if (dest)
memcpy(dest - 1, "\nbmode - getprisec", 19);
size += 18;
return size;
}
__weak int boot_mode_getprisec(void)
{
return 0;
}
static int do_boot_mode(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -62,6 +72,8 @@ static int do_boot_mode(struct cmd_tbl *cmdtp, int flag, int argc,
if (argc < 2)
return CMD_RET_USAGE;
if (!strcmp(argv[1], "getprisec"))
return boot_mode_getprisec();
p = search_modes(argv[1]);
if (!p)
return CMD_RET_USAGE;

30
arch/arm/mach-imx/init.c
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@@ -103,15 +103,29 @@ void init_src(void)
#ifdef CONFIG_CMD_BMODE
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;
#ifdef CONFIG_MX6
const u32 persist_sec = IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT;
const u32 bmode = IMX6_SRC_GPR10_BMODE;
#elif CONFIG_MX7
const u32 persist_sec = IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT;
const u32 bmode = IMX7_SRC_GPR10_BMODE;
#endif
struct src *psrc = (struct src *)SRC_BASE_ADDR;
writel(cfg_val, &psrc->gpr9);
reg = readl(&psrc->gpr10);
if (cfg_val)
reg |= IMX6_SRC_GPR10_BMODE;
else
reg &= ~IMX6_SRC_GPR10_BMODE;
writel(reg, &psrc->gpr10);
unsigned reg;
if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT)
clrbits_le32(&psrc->gpr10, persist_sec);
else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT)
setbits_le32(&psrc->gpr10, persist_sec);
else {
writel(cfg_val, &psrc->gpr9);
reg = readl(&psrc->gpr10);
if (cfg_val)
reg |= bmode;
else
reg &= ~bmode;
writel(reg, &psrc->gpr10);
}
}
#endif

134
arch/arm/mach-imx/mx6/Kconfig
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@@ -15,54 +15,64 @@ config MX6
select GPT_TIMER if !MX6UL && !MX6ULL
imply CMD_FUSE
choice
prompt "i.MX6 SoC select"
config MX6D
bool
bool "i.MX 6Dual SoC support"
select HAS_CAAM
select MX6_SMP
config MX6DL
bool
bool "i.MX 6DualLite SoC support"
select HAS_CAAM
select MX6_SMP
config MX6Q
bool
bool "i.MX 6Quad SoC support"
select HAS_CAAM
select MX6_SMP
config MX6QDL
bool
bool "i.MX 6Dual and 6Quad SoC support"
select HAS_CAAM
select MX6_SMP
config MX6S
bool
bool "i.MX 6Solo SoC support"
select HAS_CAAM
config MX6SL
bool
bool "i.MX 6SoloLite SoC support"
config MX6SX
bool
bool "i.MX 6SoloX SoC support"
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
config MX6SLL
bool
bool "i.MX 6SLL SoC support"
select ROM_UNIFIED_SECTIONS
config MX6UL
bool
bool "i.MX 6UltraLite SoC support"
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
select SYS_L2CACHE_OFF
config MX6ULL
bool "i.MX 6ULL SoC support"
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
select SYS_L2CACHE_OFF
endchoice
config MX6UL_LITESOM
bool
select DM
select DM_THERMAL
select MX6UL
select SUPPORT_SPL
imply CMD_DM
@@ -73,7 +83,6 @@ config MX6UL_OPOS6UL
select DM_GPIO
select DM_MMC
select DM_THERMAL
select MX6UL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
select SPL_PINCTRL if SPL
@@ -81,12 +90,6 @@ config MX6UL_OPOS6UL
select SUPPORT_SPL
imply CMD_DM
config MX6ULL
bool
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
select SYS_L2CACHE_OFF
config MX6_OCRAM_256KB
bool "Support 256KB OCRAM"
depends on MX6D || MX6Q
@@ -110,14 +113,14 @@ choice
config TARGET_ADVANTECH_DMS_BA16
bool "Advantech dms-ba16"
depends on MX6Q
select BOARD_LATE_INIT
select MX6Q
imply CMD_SATA
config TARGET_APALIS_IMX6
bool "Toradex Apalis iMX6 board"
depends on MX6Q
select BOARD_LATE_INIT
select MX6Q
select DM
select DM_SERIAL
select DM_THERMAL
@@ -127,8 +130,8 @@ config TARGET_APALIS_IMX6
config TARGET_ARISTAINETOS2
bool "aristainetos2"
depends on MX6DL
select BOARD_LATE_INIT
select MX6DL
select SYS_I2C_MXC
select MXC_UART
select FEC_MXC
@@ -138,8 +141,8 @@ config TARGET_ARISTAINETOS2
config TARGET_ARISTAINETOS2B
bool "Support aristainetos2-revB"
depends on MX6DL
select BOARD_LATE_INIT
select MX6DL
select SYS_I2C_MXC
select MXC_UART
select FEC_MXC
@@ -149,8 +152,8 @@ config TARGET_ARISTAINETOS2B
config TARGET_ARISTAINETOS2BCSL
bool "Support aristainetos2-revB CSL"
depends on MX6DL
select BOARD_LATE_INIT
select MX6DL
select SYS_I2C_MXC
select MXC_UART
select FEC_MXC
@@ -160,8 +163,8 @@ config TARGET_ARISTAINETOS2BCSL
config TARGET_ARISTAINETOS2C
bool "Support aristainetos2-revC"
depends on MX6DL
select BOARD_LATE_INIT
select MX6DL
select SYS_I2C_MXC
select MXC_UART
select FEC_MXC
@@ -171,20 +174,20 @@ config TARGET_ARISTAINETOS2C
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
depends on MX6QDL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6QDL
select SUPPORT_SPL
imply CMD_DM
config TARGET_CM_FX6
bool "CM-FX6"
depends on MX6QDL
select BOARD_LATE_INIT
select DM
select DM_GPIO
select DM_SERIAL
select MX6QDL
select SUPPORT_SPL
imply CMD_DM
@@ -199,14 +202,14 @@ config TARGET_COLIBRI_IMX6
config TARGET_COLIBRI_IMX6ULL
bool "Toradex Colibri iMX6ULL"
depends on MX6ULL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6ULL
config TARGET_DART_6UL
bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
select MX6ULL
depends on MX6ULL
select DM
select DM_ETH
select DM_GPIO
@@ -218,17 +221,18 @@ config TARGET_DART_6UL
config TARGET_DHCOMIMX6
bool "dh_imx6"
depends on MX6QDL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6QDL
select SUPPORT_SPL
imply CMD_DM
imply CMD_SPL
config TARGET_DISPLAY5
bool "LWN DISPLAY5 board"
depends on MX6Q
select DM
select DM_ETH
select DM_I2C
@@ -246,12 +250,12 @@ config TARGET_EMBESTMX6BOARDS
config TARGET_GE_BX50V3
bool "General Electric Bx50v3"
depends on MX6Q
select BOARD_LATE_INIT
select MX6Q
config TARGET_GW_VENTANA
bool "gw_ventana"
select MX6QDL
depends on MX6QDL
select SUPPORT_SPL
imply CMD_SATA
imply CMD_SPL
@@ -272,7 +276,7 @@ config TARGET_KOSAGI_NOVENA
config TARGET_MCCMON6
bool "mccmon6"
select MX6QDL
depends on MX6QDL
select SUPPORT_SPL
select DM
select DM_GPIO
@@ -284,13 +288,13 @@ config TARGET_MCCMON6
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
depends on MX6QDL
select BOARD_LATE_INIT
select MX6QDL
select SUPPORT_SPL
config TARGET_MX6LOGICPD
bool "Logic PD i.MX6 SOM"
select MX6Q
depends on MX6Q
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
@@ -305,6 +309,7 @@ config TARGET_MX6LOGICPD
config TARGET_MX6MEMCAL
bool "mx6memcal"
depends on MX6QDL
select SUPPORT_SPL
help
The mx6memcal board is a virtual board that can be used to validate
@@ -316,6 +321,7 @@ config TARGET_MX6QARM2
config TARGET_MX6DL_MAMOJ
bool "Support BTicino Mamoj"
depends on MX6QDL
select DM
select DM_ETH
select DM_GPIO
@@ -324,7 +330,6 @@ config TARGET_MX6DL_MAMOJ
select DM_PMIC
select DM_PMIC_PFUZE100
select DM_THERMAL
select MX6QDL
select OF_CONTROL
select PINCTRL
select SPL
@@ -348,6 +353,7 @@ config TARGET_MX6DL_MAMOJ
config TARGET_MX6Q_ENGICAM
bool "Support Engicam i.Core(RQS)"
depends on MX6QDL
select BOARD_LATE_INIT
select DM
select DM_ETH
@@ -355,7 +361,6 @@ config TARGET_MX6Q_ENGICAM
select DM_I2C
select DM_MMC
select DM_THERMAL
select MX6QDL
select OF_CONTROL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
@@ -367,75 +372,76 @@ config TARGET_MX6Q_ENGICAM
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
depends on MX6QDL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6QDL
select SUPPORT_SPL
imply CMD_DM
config TARGET_MX6SABRESD
bool "mx6sabresd"
depends on MX6QDL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6QDL
select SUPPORT_SPL
imply CMD_DM
config TARGET_MX6SLEVK
bool "mx6slevk"
select MX6SL
depends on MX6SL
select SUPPORT_SPL
config TARGET_MX6SLLEVK
bool "mx6sll evk"
depends on MX6SLL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6SLL
imply CMD_DM
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
depends on MX6SX
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6SX
select SUPPORT_SPL
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
depends on MX6SX
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6SX
imply CMD_DM
config TARGET_MX6UL_9X9_EVK
bool "mx6ul_9x9_evk"
depends on MX6UL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6UL
select SUPPORT_SPL
imply CMD_DM
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
depends on MX6UL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6UL
select SUPPORT_SPL
imply CMD_DM
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
depends on MX6UL
select BOARD_LATE_INIT
select DM
select DM_ETH
@@ -443,7 +449,6 @@ config TARGET_MX6UL_ENGICAM
select DM_I2C
select DM_MMC
select DM_THERMAL
select MX6UL
select OF_CONTROL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
@@ -454,15 +459,15 @@ config TARGET_MX6UL_ENGICAM
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
depends on MX6ULL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6ULL
imply CMD_DM
config TARGET_MYS_6ULX
bool "MYiR MYS-6ULX"
select MX6ULL
depends on MX6ULL
select DM
select DM_ETH
select DM_GPIO
@@ -474,14 +479,15 @@ config TARGET_MYS_6ULX
config TARGET_NITROGEN6X
bool "nitrogen6x"
depends on MX6DL || MX6Q || MX6QDL || MX6S
imply USB_ETHER_ASIX
imply USB_ETHER_MCS7830
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
select MX6QDL
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"
depends on MX6UL
select MX6UL_OPOS6UL
config TARGET_OT1200
@@ -491,23 +497,24 @@ config TARGET_OT1200
config TARGET_PICO_IMX6
bool "PICO-IMX6"
depends on MX6QDL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6QDL
select SUPPORT_SPL
imply CMD_DM
config TARGET_PICO_IMX6UL
bool "PICO-IMX6UL-EMMC"
select MX6UL
depends on MX6UL
select DM
select SUPPORT_SPL
imply CMD_DM
config TARGET_LITEBOARD
bool "Grinn liteBoard (i.MX6UL)"
depends on MX6UL
select BOARD_LATE_INIT
select MX6UL_LITESOM
@@ -521,22 +528,22 @@ config TARGET_PLATINUM_TITANIUM
config TARGET_PCM058
bool "Phytec PCM058 i.MX6 Quad"
depends on MX6Q
select BOARD_LATE_INIT
select SUPPORT_SPL
select MX6Q
select DM
select OF_CONTROL
imply CMD_DM
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
depends on MX6QDL
select BOARD_LATE_INIT
select MX6QDL
select SUPPORT_SPL
config TARGET_PCL063
bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
select MX6UL
depends on MX6UL
select DM
select DM_ETH
select DM_GPIO
@@ -548,7 +555,7 @@ config TARGET_PCL063
config TARGET_PCL063_ULL
bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)"
select MX6ULL
depends on MX6ULL
select DM
select DM_ETH
select DM_GPIO
@@ -563,11 +570,12 @@ config TARGET_SECOMX6
config TARGET_SKSIMX6
bool "sks-imx6"
depends on MX6QDL
select SUPPORT_SPL
config TARGET_SOMLABS_VISIONSOM_6ULL
bool "visionsom-6ull"
select MX6ULL
depends on MX6ULL
select BOARD_LATE_INIT
select DM
select DM_ETH
@@ -579,12 +587,15 @@ config TARGET_SOMLABS_VISIONSOM_6ULL
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
depends on MX6Q
config TARGET_TITANIUM
bool "titanium"
depends on MX6Q
config TARGET_KP_IMX6Q_TPC
bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
depends on MX6QDL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
@@ -598,7 +609,6 @@ config TARGET_KP_IMX6Q_TPC
select DM_I2C
select DM_GPIO
select DM_USB
select MX6QDL
select SUPPORT_SPL
select SPL_SEPARATE_BSS if SPL
imply CMD_DM
@@ -621,45 +631,45 @@ config TARGET_TQMA6
config TARGET_UDOO
bool "udoo"
depends on MX6QDL
select BOARD_LATE_INIT
select MX6QDL
select SUPPORT_SPL
config TARGET_UDOO_NEO
bool "UDOO Neo"
depends on MX6SX
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6SX
select SUPPORT_SPL
imply CMD_DM
config TARGET_SOFTING_VINING_2000
bool "Softing VIN|ING 2000"
depends on MX6SX
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6SX
select SUPPORT_SPL
imply CMD_DM
config TARGET_WANDBOARD
bool "wandboard"
depends on MX6QDL
select BOARD_LATE_INIT
select MX6QDL
select SUPPORT_SPL
config TARGET_WARP
bool "WaRP"
depends on MX6SL
select BOARD_LATE_INIT
select MX6SL
config TARGET_XPRESS
bool "CCV xPress"
depends on MX6UL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX6UL
select SUPPORT_SPL
imply CMD_DM
@@ -681,8 +691,8 @@ config TARGET_ZC5601
config TARGET_BRPPT2
bool "brppt2"
depends on MX6QDL
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select SPL_OF_LIBFDT
select DM

9
arch/arm/mach-imx/mx7/ddr.c
View File

@@ -106,6 +106,15 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
&ddr_phy_regs->cmd_sdll_con0);
writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
writel(ddr_phy_regs_val->cmd_deskew_con0,
&ddr_phy_regs->cmd_deskew_con0);
writel(ddr_phy_regs_val->cmd_deskew_con1,
&ddr_phy_regs->cmd_deskew_con1);
writel(ddr_phy_regs_val->cmd_deskew_con2,
&ddr_phy_regs->cmd_deskew_con2);
writel(ddr_phy_regs_val->cmd_deskew_con3,
&ddr_phy_regs->cmd_deskew_con3);
writel(ddr_phy_regs_val->cmd_lvl_con0, &ddr_phy_regs->cmd_lvl_con0);
/* calibration */
for (i = 0; i < calib_param->num_val; i++)

17
arch/arm/mach-imx/mx7/soc.c
View File

@@ -13,6 +13,7 @@
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <env.h>
@@ -410,6 +411,22 @@ void s_init(void)
return;
}
#ifndef CONFIG_SPL_BUILD
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
{"primary", MAKE_CFGVAL_PRIMARY_BOOT},
{"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
{NULL, 0},
};
int boot_mode_getprisec(void)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
}
#endif
void reset_misc(void)
{
#ifndef CONFIG_SPL_BUILD

23
arch/arm/mach-octeontx/Kconfig Normal file
View File

@@ -0,0 +1,23 @@
if ARCH_OCTEONTX
choice
prompt "OcteonTX board select"
optional
config TARGET_OCTEONTX_81XX
bool "Marvell OcteonTX CN81XX"
config TARGET_OCTEONTX_83XX
bool "Marvell OcteonTX CN83XX"
endchoice
config SYS_SOC
string
default "octeontx"
config SYS_PCI_64BIT
bool
default y
endif

9
arch/arm/mach-octeontx/Makefile Normal file
View File

@@ -0,0 +1,9 @@
#/* SPDX-License-Identifier: GPL-2.0
# *
# * Copyright (C) 2018 Marvell International Ltd.
# *
# * https://spdx.org/licenses
# */
obj-y += lowlevel_init.o clock.o cpu.o

35
arch/arm/mach-octeontx/clock.c Normal file
View File

@@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/board.h>
#include <asm/arch/clock.h>
/**
* Returns the I/O clock speed in Hz
*/
u64 octeontx_get_io_clock(void)
{
union rst_boot rst_boot;
rst_boot.u = readq(RST_BOOT);
return rst_boot.s.pnr_mul * PLL_REF_CLK;
}
/**
* Returns the core clock speed in Hz
*/
u64 octeontx_get_core_clock(void)
{
union rst_boot rst_boot;
rst_boot.u = readq(RST_BOOT);
return rst_boot.s.c_mul * PLL_REF_CLK;
}

76
arch/arm/mach-octeontx/cpu.c Normal file
View File

@@ -0,0 +1,76 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <common.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch/board.h>
DECLARE_GLOBAL_DATA_PTR;
#define OTX_MEM_MAP_USED 3
/* 1 for 83xx, +1 is end of list which needs to be empty */
#define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1)
static struct mm_region otx_mem_map[OTX_MEM_MAP_MAX] = {
{
.virt = 0x800000000000UL,
.phys = 0x800000000000UL,
.size = 0x40000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0x840000000000UL,
.phys = 0x840000000000UL,
.size = 0x40000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0x880000000000UL,
.phys = 0x880000000000UL,
.size = 0x40000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
}
};
struct mm_region *mem_map = otx_mem_map;
void mem_map_fill(void)
{
int banks = OTX_MEM_MAP_USED;
u32 dram_start = CONFIG_SYS_TEXT_BASE;
if (otx_is_soc(CN83XX)) {
otx_mem_map[banks].virt = 0x8c0000000000UL;
otx_mem_map[banks].phys = 0x8c0000000000UL;
otx_mem_map[banks].size = 0x40000000000UL;
otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE;
banks = banks + 1;
}
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
otx_mem_map[banks].virt = dram_start;
otx_mem_map[banks].phys = dram_start;
otx_mem_map[banks].size = gd->ram_size;
otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_NON_SHARE;
banks = banks + 1;
}
}
u64 get_page_table_size(void)
{
return 0x80000;
}
void reset_cpu(ulong addr)
{
}

33
arch/arm/mach-octeontx/lowlevel_init.S Normal file
View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
.align 8
.global fdt_base_addr
fdt_base_addr:
.dword 0x0
.global save_boot_params
save_boot_params:
/* Read FDT base from x1 register passed by ATF */
adr x21, fdt_base_addr
str x1, [x21]
/* Returns */
b save_boot_params_ret
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
/* any lowlevel init should go here */
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)

23
arch/arm/mach-octeontx2/Kconfig Normal file
View File

@@ -0,0 +1,23 @@
if ARCH_OCTEONTX2
choice
prompt "OcteonTX2 board select"
optional
config TARGET_OCTEONTX2_95XX
bool "Marvell OcteonTX2 CN95XX"
config TARGET_OCTEONTX2_96XX
bool "Marvell OcteonTX2 CN96XX"
endchoice
config SYS_SOC
string
default "octeontx2"
config SYS_PCI_64BIT
bool
default y
endif

9
arch/arm/mach-octeontx2/Makefile Normal file
View File

@@ -0,0 +1,9 @@
#/*
# * Copyright (C) 2018 Marvell International Ltd.
# *
# * SPDX-License-Identifier: GPL-2.0
# * https://spdx.org/licenses
# */
obj-y += lowlevel_init.o clock.o cpu.o

35
arch/arm/mach-octeontx2/clock.c Normal file
View File

@@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/board.h>
#include <asm/arch/clock.h>
/**
* Returns the I/O clock speed in Hz
*/
u64 octeontx_get_io_clock(void)
{
union rst_boot rst_boot;
rst_boot.u = readq(RST_BOOT);
return rst_boot.s.pnr_mul * PLL_REF_CLK;
}
/**
* Returns the core clock speed in Hz
*/
u64 octeontx_get_core_clock(void)
{
union rst_boot rst_boot;
rst_boot.u = readq(RST_BOOT);
return rst_boot.s.c_mul * PLL_REF_CLK;
}

4
arch/arm/mach-octeontx2/config.mk Normal file
View File

@@ -0,0 +1,4 @@
ifeq ($(CONFIG_ARCH_OCTEONTX2),y)
PLATFORM_CPPFLAGS += $(call cc-option,-march=armv8.2-a,)
PLATFORM_CPPFLAGS += $(call cc-option,-mtune=octeontx2,)
endif

72
arch/arm/mach-octeontx2/cpu.c Normal file
View File

@@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <common.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch/board.h>
DECLARE_GLOBAL_DATA_PTR;
#define OTX2_MEM_MAP_USED 4
/* +1 is end of list which needs to be empty */
#define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
{
.virt = 0x800000000000UL,
.phys = 0x800000000000UL,
.size = 0x40000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0x840000000000UL,
.phys = 0x840000000000UL,
.size = 0x40000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0x880000000000UL,
.phys = 0x880000000000UL,
.size = 0x40000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0x8c0000000000UL,
.phys = 0x8c0000000000UL,
.size = 0x40000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
}
};
struct mm_region *mem_map = otx2_mem_map;
void mem_map_fill(void)
{
int banks = OTX2_MEM_MAP_USED;
u32 dram_start = CONFIG_SYS_TEXT_BASE;
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
otx2_mem_map[banks].virt = dram_start;
otx2_mem_map[banks].phys = dram_start;
otx2_mem_map[banks].size = gd->ram_size;
otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_NON_SHARE;
banks = banks + 1;
}
}
u64 get_page_table_size(void)
{
return 0x80000;
}
void reset_cpu(ulong addr)
{
}

33
arch/arm/mach-octeontx2/lowlevel_init.S Normal file
View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
.align 8
.global fdt_base_addr
fdt_base_addr:
.dword 0x0
.global save_boot_params
save_boot_params:
/* Read FDT base from x1 register passed by ATF */
adr x21, fdt_base_addr
str x1, [x21]
/* Returns */
b save_boot_params_ret
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
/* any lowlevel init should go here */
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)

5
arch/sandbox/dts/test.dts
View File

@@ -666,8 +666,9 @@
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
0x01000000 0 0x40000000 0x40000000 0 0x2000>;
ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
0x01000000 0 0x40000000 0x40000000 0 0x2000>;
sandbox,dev-info = <0x08 0x00 0x1234 0x5678
0x0c 0x00 0x1234 0x5678
0x10 0x00 0x1234 0x5678>;

14
board/Marvell/octeontx/Kconfig Normal file
View File

@@ -0,0 +1,14 @@
if TARGET_OCTEONTX_81XX || TARGET_OCTEONTX_83XX
config SYS_VENDOR
string
default "Marvell"
config SYS_BOARD
string
default "octeontx"
config SYS_CONFIG_NAME
default "octeontx_common"
endif

8
board/Marvell/octeontx/MAINTAINERS Normal file
View File

@@ -0,0 +1,8 @@
OCTEONTX BOARD
M: Aaron Williams <awilliams@marvell.com>
S: Maintained
F: board/Marvell/octeontx/
F: include/configs/octeontx_81xx.h
F: include/configs/octeontx_83xx.h
F: configs/octeontx_81xx_defconfig
F: configs/octeontx_83xx_defconfig

9
board/Marvell/octeontx/Makefile Normal file
View File

@@ -0,0 +1,9 @@
#/*
# * Copyright (C) 2018 Marvell International Ltd.
# *
# * SPDX-License-Identifier: GPL-2.0
# * https://spdx.org/licenses
# */
obj-y := board.o smc.o soc-utils.o
obj-$(CONFIG_OF_LIBFDT) += board-fdt.o

311
board/Marvell/octeontx/board-fdt.c Normal file
View File

@@ -0,0 +1,311 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <errno.h>
#include <env.h>
#include <log.h>
#include <net.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <linux/libfdt.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <asm/arch/board.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static int fdt_get_mdio_bus(const void *fdt, int phy_offset)
{
int node, bus = -1;
const u64 *reg;
u64 addr;
if (phy_offset < 0)
return -1;
/* obtain mdio node and get the reg prop */
node = fdt_parent_offset(fdt, phy_offset);
if (node < 0)
return -1;
reg = fdt_getprop(fdt, node, "reg", NULL);
addr = fdt64_to_cpu(*reg);
bus = (addr & (1 << 7)) ? 1 : 0;
return bus;
}
static int fdt_get_phy_addr(const void *fdt, int phy_offset)
{
const u32 *reg;
int addr = -1;
if (phy_offset < 0)
return -1;
reg = fdt_getprop(fdt, phy_offset, "reg", NULL);
addr = fdt32_to_cpu(*reg);
return addr;
}
void fdt_parse_phy_info(void)
{
const void *fdt = gd->fdt_blob;
int offset = 0, node, bgx_id = 0, lmacid = 0;
const u32 *val;
char bgxname[24];
int len, rgx_id = 0, eth_id = 0;
int phandle, phy_offset;
int subnode, i;
int bdknode;
bdknode = fdt_path_offset(fdt, "/cavium,bdk");
if (bdknode < 0) {
printf("%s: bdk node is missing from device tree: %s\n",
__func__, fdt_strerror(bdknode));
}
offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge");
if (offset < 1)
return;
for (bgx_id = 0; bgx_id < MAX_BGX_PER_NODE; bgx_id++) {
int phy_addr[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1};
bool autoneg_dis[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
int mdio_bus[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1};
bool lmac_reg[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
bool lmac_enable[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx_id);
node = fdt_subnode_offset(fdt, offset, bgxname);
if (node < 0) {
/* check if it is rgx node */
snprintf(bgxname, sizeof(bgxname), "rgx%d", rgx_id);
node = fdt_subnode_offset(fdt, offset, bgxname);
if (node < 0) {
debug("bgx%d/rgx0 node not found\n", bgx_id);
return;
}
}
debug("bgx%d node found\n", bgx_id);
/*
* loop through each of the bgx/rgx nodes
* to find PHY nodes
*/
fdt_for_each_subnode(subnode, fdt, node) {
/* Check for reg property */
val = fdt_getprop(fdt, subnode, "reg", &len);
if (val) {
debug("lmacid = %d\n", lmacid);
lmac_reg[lmacid] = 1;
}
/* check for phy-handle property */
val = fdt_getprop(fdt, subnode, "phy-handle", &len);
if (val) {
phandle = fdt32_to_cpu(*val);
if (!phandle) {
debug("phandle not valid %d\n", lmacid);
} else {
phy_offset = fdt_node_offset_by_phandle
(fdt, phandle);
phy_addr[lmacid] = fdt_get_phy_addr
(fdt, phy_offset);
mdio_bus[lmacid] = fdt_get_mdio_bus
(fdt, phy_offset);
}
} else {
debug("phy-handle prop not found %d\n",
lmacid);
}
/* check for autonegotiation property */
val = fdt_getprop(fdt, subnode,
"cavium,disable-autonegotiation",
&len);
if (val)
autoneg_dis[lmacid] = 1;
eth_id++;
lmacid++;
}
for (i = 0; i < MAX_LMAC_PER_BGX; i++) {
const char *str;
snprintf(bgxname, sizeof(bgxname),
"BGX-ENABLE.N0.BGX%d.P%d", bgx_id, i);
if (bdknode >= 0) {
str = fdt_getprop(fdt, bdknode,
bgxname, &len);
if (str)
lmac_enable[i] =
simple_strtol(str, NULL,
10);
}
}
lmacid = 0;
bgx_set_board_info(bgx_id, mdio_bus, phy_addr,
autoneg_dis, lmac_reg, lmac_enable);
}
}
static int fdt_get_bdk_node(void)
{
int node, ret;
const void *fdt = gd->fdt_blob;
if (!fdt) {
printf("ERROR: %s: no valid device tree found\n", __func__);
return 0;
}
ret = fdt_check_header(fdt);
if (ret < 0) {
printf("fdt: %s\n", fdt_strerror(ret));
return 0;
}
node = fdt_path_offset(fdt, "/cavium,bdk");
if (node < 0) {
printf("%s: /cavium,bdk is missing from device tree: %s\n",
__func__, fdt_strerror(node));
return 0;
}
return node;
}
const char *fdt_get_board_serial(void)
{
const void *fdt = gd->fdt_blob;
int node, len = 64;
const char *str = NULL;
node = fdt_get_bdk_node();
if (!node)
return NULL;
str = fdt_getprop(fdt, node, "BOARD-SERIAL", &len);
if (!str)
printf("Error: cannot retrieve board serial from fdt\n");
return str;
}
const char *fdt_get_board_revision(void)
{
const void *fdt = gd->fdt_blob;
int node, len = 64;
const char *str = NULL;
node = fdt_get_bdk_node();
if (!node)
return NULL;
str = fdt_getprop(fdt, node, "BOARD-REVISION", &len);
if (!str)
printf("Error: cannot retrieve board revision from fdt\n");
return str;
}
const char *fdt_get_board_model(void)
{
const void *fdt = gd->fdt_blob;
int node, len = 16;
const char *str = NULL;
node = fdt_get_bdk_node();
if (!node)
return NULL;
str = fdt_getprop(fdt, node, "BOARD-MODEL", &len);
if (!str)
printf("Error: cannot retrieve board model from fdt\n");
return str;
}
void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth)
{
const void *fdt = gd->fdt_blob;
const char *mac = NULL;
int offset = 0, node, len;
int subnode, i = 0;
char bgxname[24];
offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge");
if (offset < 0) {
printf("%s couldn't find mrml bridge node in fdt\n",
__func__);
return;
}
if (bgx == 2 && otx_is_soc(CN81XX)) {
snprintf(bgxname, sizeof(bgxname), "rgx%d", 0);
lmac = 0;
} else {
snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx);
}
node = fdt_subnode_offset(fdt, offset, bgxname);
fdt_for_each_subnode(subnode, fdt, node) {
if (i++ != lmac)
continue;
/* check for local-mac-address */
mac = fdt_getprop(fdt, subnode, "local-mac-address", &len);
if (mac) {
debug("%s mac %pM\n", __func__, mac);
memcpy(eth, mac, ARP_HLEN);
} else {
memset(eth, 0, ARP_HLEN);
}
debug("%s eth %pM\n", __func__, eth);
return;
}
}
int arch_fixup_memory_node(void *blob)
{
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
/* remove "cavium, bdk" node from DT */
int ret = 0, offset;
ret = fdt_check_header(blob);
if (ret < 0) {
printf("ERROR: %s\n", fdt_strerror(ret));
return ret;
}
if (blob) {
offset = fdt_path_offset(blob, "/cavium,bdk");
if (offset < 0) {
printf("ERROR: FDT BDK node not found\n");
return offset;
}
/* delete node */
ret = fdt_del_node(blob, offset);
if (ret < 0) {
printf("WARNING : could not remove bdk node\n");
return ret;
}
debug("%s deleted bdk node\n", __func__);
}
return 0;
}
/**
* Return the FDT base address that was passed by ATF
*
* @return FDT base address received from ATF in x1 register
*/
void *board_fdt_blob_setup(void)
{
return (void *)fdt_base_addr;
}

152
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <env.h>
#include <init.h>
#include <log.h>
#include <netdev.h>
#include <pci_ids.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/arch/smc.h>
#include <asm/arch/soc.h>
#include <asm/arch/board.h>
#include <dm/util.h>
DECLARE_GLOBAL_DATA_PTR;
void octeontx_cleanup_ethaddr(void)
{
char ename[32];
for (int i = 0; i < 20; i++) {
sprintf(ename, i ? "eth%daddr" : "ethaddr", i);
if (env_get(ename))
env_set(ename, NULL);
}
}
int octeontx_board_has_pmp(void)
{
return (otx_is_board("sff8104") || otx_is_board("nas8104"));
}
int board_early_init_r(void)
{
pci_init();
return 0;
}
int board_init(void)
{
if (IS_ENABLED(CONFIG_NET_OCTEONTX))
fdt_parse_phy_info();
return 0;
}
int timer_init(void)
{
return 0;
}
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
mem_map_fill();
return 0;
}
void board_late_probe_devices(void)
{
struct udevice *dev;
int err, bgx_cnt, i;
/* Probe MAC(BGX) and NIC PF devices before Network stack init */
bgx_cnt = otx_is_soc(CN81XX) ? 2 : 4;
for (i = 0; i < bgx_cnt; i++) {
err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVICE_ID_CAVIUM_BGX, i, &dev);
if (err)
debug("%s BGX%d device not found\n", __func__, i);
}
if (otx_is_soc(CN81XX)) {
err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVICE_ID_CAVIUM_RGX, 0, &dev);
if (err)
debug("%s RGX device not found\n", __func__);
}
err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVICE_ID_CAVIUM_NIC, 0, &dev);
if (err)
debug("NIC PF device not found\n");
}
/**
* Board late initialization routine.
*/
int board_late_init(void)
{
char boardname[32];
char boardserial[150], boardrev[150];
bool save_env = false;
const char *str;
/*
* Try to cleanup ethaddr env variables, this is needed
* as with each boot, configuration of network interfaces can change.
*/
octeontx_cleanup_ethaddr();
snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model());
env_set("prompt", boardname);
set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr));
str = fdt_get_board_revision();
if (str) {
snprintf(boardrev, sizeof(boardrev), "%s", str);
if (env_get("boardrev") &&
strcmp(boardrev, env_get("boardrev")))
save_env = true;
env_set("boardrev", boardrev);
}
str = fdt_get_board_serial();
if (str) {
snprintf(boardserial, sizeof(boardserial), "%s", str);
if (env_get("serial#") &&
strcmp(boardserial, env_get("serial#")))
save_env = true;
env_set("serial#", boardserial);
}
if (IS_ENABLED(CONFIG_NET_OCTEONTX))
board_late_probe_devices();
if (save_env)
env_save();
return 0;
}
/*
* Invoked before relocation, so limit to stack variables.
*/
int checkboard(void)
{
printf("Board: %s\n", fdt_get_board_model());
return 0;
}

25
board/Marvell/octeontx/smc.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/arch/smc.h>
DECLARE_GLOBAL_DATA_PTR;
ssize_t smc_dram_size(unsigned int node)
{
struct pt_regs regs;
regs.regs[0] = OCTEONTX_DRAM_SIZE;
regs.regs[1] = node;
smc_call(&regs);
return regs.regs[0];
}

50
board/Marvell/octeontx/soc-utils.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <dm.h>
#include <dm/util.h>
#include <errno.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
#include <asm/arch/board.h>
int read_platform(void)
{
int plat = PLATFORM_HW;
const char *model = fdt_get_board_model();
if (model && !strncmp(model, "ASIM-", 5))
plat = PLATFORM_ASIM;
if (model && !strncmp(model, "EMUL-", 5))
plat = PLATFORM_EMULATOR;
return plat;
}
static inline u64 read_midr(void)
{
u64 result;
asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
return result;
}
u8 read_partnum(void)
{
return ((read_midr() >> 4) & 0xFF);
}
const char *read_board_name(void)
{
return fdt_get_board_model();
}
bool read_alt_pkg(void)
{
return false;
}

14
board/Marvell/octeontx2/Kconfig Normal file
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if TARGET_OCTEONTX2_95XX || TARGET_OCTEONTX2_96XX
config SYS_VENDOR
string
default "Marvell"
config SYS_BOARD
string
default "octeontx2"
config SYS_CONFIG_NAME
default "octeontx2_common"
endif

8
board/Marvell/octeontx2/MAINTAINERS Normal file
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OCTEONTX2 BOARD
M: Aaron Williams <awilliams@marvell.com>
S: Maintained
F: board/Marvell/octeontx2/
F: include/configs/octeontx2_96xx.h
F: include/configs/octeontx2_95xx.h
F: configs/octeontx2_96xx_defconfig
F: configs/octeontx2_95xx_defconfig

9
board/Marvell/octeontx2/Makefile Normal file
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#/* SPDX-License-Identifier: GPL-2.0
# *
# * Copyright (C) 2018 Marvell International Ltd.
# *
# * https://spdx.org/licenses
# */
obj-y := board.o smc.o soc-utils.o
obj-$(CONFIG_OF_LIBFDT) += board-fdt.o

221
board/Marvell/octeontx2/board-fdt.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <errno.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <log.h>
#include <linux/compiler.h>
#include <linux/libfdt.h>
#include <asm/arch/board.h>
#include <asm/arch/smc.h>
#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
static int fdt_get_bdk_node(void)
{
int node, ret;
const void *fdt = gd->fdt_blob;
if (!fdt) {
printf("ERROR: %s: no valid device tree found\n", __func__);
return 0;
}
ret = fdt_check_header(fdt);
if (ret < 0) {
printf("fdt: %s\n", fdt_strerror(ret));
return 0;
}
node = fdt_path_offset(fdt, "/cavium,bdk");
if (node < 0) {
printf("%s: /cavium,bdk is missing from device tree: %s\n",
__func__, fdt_strerror(node));
return 0;
}
return node;
}
u64 fdt_get_board_mac_addr(void)
{
int node, len = 16;
const char *str = NULL;
const void *fdt = gd->fdt_blob;
u64 mac_addr = 0;
node = fdt_get_bdk_node();
if (!node)
return mac_addr;
str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS", &len);
if (str)
mac_addr = simple_strtol(str, NULL, 16);
return mac_addr;
}
int fdt_get_board_mac_cnt(void)
{
int node, len = 16;
const char *str = NULL;
const void *fdt = gd->fdt_blob;
int mac_count = 0;
node = fdt_get_bdk_node();
if (!node)
return mac_count;
str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS-NUM", &len);
if (str) {
mac_count = simple_strtol(str, NULL, 10);
if (!mac_count)
mac_count = simple_strtol(str, NULL, 16);
debug("fdt: MAC_NUM %d\n", mac_count);
} else {
printf("Error: cannot retrieve mac count prop from fdt\n");
}
str = fdt_getprop(gd->fdt_blob, node, "BOARD-MAC-ADDRESS-NUM-OVERRIDE",
&len);
if (str) {
if (simple_strtol(str, NULL, 10) >= 0)
mac_count = simple_strtol(str, NULL, 10);
debug("fdt: MAC_NUM %d\n", mac_count);
} else {
printf("Error: cannot retrieve mac num override prop\n");
}
return mac_count;
}
const char *fdt_get_board_serial(void)
{
const void *fdt = gd->fdt_blob;
int node, len = 64;
const char *str = NULL;
node = fdt_get_bdk_node();
if (!node)
return NULL;
str = fdt_getprop(fdt, node, "BOARD-SERIAL", &len);
if (!str)
printf("Error: cannot retrieve board serial from fdt\n");
return str;
}
const char *fdt_get_board_revision(void)
{
const void *fdt = gd->fdt_blob;
int node, len = 64;
const char *str = NULL;
node = fdt_get_bdk_node();
if (!node)
return NULL;
str = fdt_getprop(fdt, node, "BOARD-REVISION", &len);
if (!str)
printf("Error: cannot retrieve board revision from fdt\n");
return str;
}
const char *fdt_get_board_model(void)
{
int node, len = 16;
const char *str = NULL;
const void *fdt = gd->fdt_blob;
node = fdt_get_bdk_node();
if (!node)
return NULL;
str = fdt_getprop(fdt, node, "BOARD-MODEL", &len);
if (!str)
printf("Error: cannot retrieve board model from fdt\n");
return str;
}
int arch_fixup_memory_node(void *blob)
{
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
int nodeoff, node, ret, i;
const char *temp;
static const char * const
octeontx_brd_nodes[] = {"BOARD-MODEL",
"BOARD-SERIAL",
"BOARD-MAC-ADDRESS",
"BOARD-REVISION",
"BOARD-MAC-ADDRESS-NUM"
};
char nodes[ARRAY_SIZE(octeontx_brd_nodes)][32];
ret = fdt_check_header(blob);
if (ret < 0) {
printf("ERROR: %s\n", fdt_strerror(ret));
return ret;
}
if (blob) {
nodeoff = fdt_path_offset(blob, "/cavium,bdk");
if (nodeoff < 0) {
printf("ERROR: FDT BDK node not found\n");
return nodeoff;
}
/* Read properties in temporary variables */
for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) {
temp = fdt_getprop(blob, nodeoff,
octeontx_brd_nodes[i], NULL);
strncpy(nodes[i], temp, sizeof(nodes[i]));
}
/* Delete cavium,bdk node */
ret = fdt_del_node(blob, nodeoff);
if (ret < 0) {
printf("WARNING : could not remove cavium, bdk node\n");
return ret;
}
debug("%s deleted 'cavium,bdk' node\n", __func__);
/*
* Add a new node at root level which would have
* necessary info
*/
node = fdt_add_subnode(blob, 0, "octeontx_brd");
if (node < 0) {
printf("Cannot create node octeontx_brd: %s\n",
fdt_strerror(node));
return -EIO;
}
/* Populate properties in node */
for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) {
if (fdt_setprop_string(blob, node,
octeontx_brd_nodes[i],
nodes[i])) {
printf("Can't set %s\n", nodes[i]);
return -EIO;
}
}
}
return 0;
}
/**
* Return the FDT base address that was passed by ATF
*
* @return FDT base address received from ATF in x1 register
*/
void *board_fdt_blob_setup(void)
{
return (void *)fdt_base_addr;
}

247
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <command.h>
#include <console.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
#include <net.h>
#include <pci_ids.h>
#include <errno.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/arch/smc.h>
#include <asm/arch/soc.h>
#include <asm/arch/board.h>
#include <dm/util.h>
DECLARE_GLOBAL_DATA_PTR;
void cleanup_env_ethaddr(void)
{
char ename[32];
for (int i = 0; i < 20; i++) {
sprintf(ename, i ? "eth%daddr" : "ethaddr", i);
if (env_get(ename))
env_set(ename, NULL);
}
}
void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr)
{
u64 tmp_mac, board_mac_addr = fdt_get_board_mac_addr();
static int board_mac_num;
board_mac_num = fdt_get_board_mac_cnt();
if ((!is_zero_ethaddr((u8 *)&board_mac_addr)) && board_mac_num) {
tmp_mac = board_mac_addr;
tmp_mac += index;
tmp_mac = swab64(tmp_mac) >> 16;
memcpy(mac_addr, (u8 *)&tmp_mac, ARP_HLEN);
board_mac_num--;
} else {
memset(mac_addr, 0, ARP_HLEN);
}
debug("%s mac %pM\n", __func__, mac_addr);
}
void board_quiesce_devices(void)
{
struct uclass *uc_dev;
int ret;
/* Removes all RVU PF devices */
ret = uclass_get(UCLASS_ETH, &uc_dev);
if (uc_dev)
ret = uclass_destroy(uc_dev);
if (ret)
printf("couldn't remove rvu pf devices\n");
if (IS_ENABLED(CONFIG_OCTEONTX2_CGX_INTF)) {
/* Bring down all cgx lmac links */
cgx_intf_shutdown();
}
/* Removes all CGX and RVU AF devices */
ret = uclass_get(UCLASS_MISC, &uc_dev);
if (uc_dev)
ret = uclass_destroy(uc_dev);
if (ret)
printf("couldn't remove misc (cgx/rvu_af) devices\n");
/* SMC call - removes all LF<->PF mappings */
smc_disable_rvu_lfs(0);
}
int board_early_init_r(void)
{
pci_init();
return 0;
}
int board_init(void)
{
return 0;
}
int timer_init(void)
{
return 0;
}
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
mem_map_fill();
return 0;
}
void board_late_probe_devices(void)
{
struct udevice *dev;
int err, cgx_cnt = 3, i;
/* Probe MAC(CGX) and NIC AF devices before Network stack init */
for (i = 0; i < cgx_cnt; i++) {
err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVICE_ID_CAVIUM_CGX, i, &dev);
if (err)
debug("%s CGX%d device not found\n", __func__, i);
}
err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVICE_ID_CAVIUM_RVU_AF, 0, &dev);
if (err)
debug("NIC AF device not found\n");
}
/**
* Board late initialization routine.
*/
int board_late_init(void)
{
char boardname[32];
char boardserial[150], boardrev[150];
long val;
bool save_env = false;
const char *str;
debug("%s()\n", __func__);
/*
* Now that pci_init initializes env device.
* Try to cleanup ethaddr env variables, this is needed
* as with each boot, configuration of QLM can change.
*/
cleanup_env_ethaddr();
snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model());
env_set("prompt", boardname);
set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr));
str = fdt_get_board_revision();
if (str) {
snprintf(boardrev, sizeof(boardrev), "%s", str);
if (env_get("boardrev") &&
strcmp(boardrev, env_get("boardrev")))
save_env = true;
env_set("boardrev", boardrev);
}
str = fdt_get_board_serial();
if (str) {
snprintf(boardserial, sizeof(boardserial), "%s", str);
if (env_get("serial#") &&
strcmp(boardserial, env_get("serial#")))
save_env = true;
env_set("serial#", boardserial);
}
val = env_get_hex("disable_ooo", 0);
smc_configure_ooo(val);
if (IS_ENABLED(CONFIG_NET_OCTEONTX2))
board_late_probe_devices();
if (save_env)
env_save();
return 0;
}
/*
* Invoked before relocation, so limit to stack variables.
*/
int checkboard(void)
{
printf("Board: %s\n", fdt_get_board_model());
return 0;
}
void board_acquire_flash_arb(bool acquire)
{
union cpc_boot_ownerx ownerx;
if (!acquire) {
ownerx.u = readl(CPC_BOOT_OWNERX(3));
ownerx.s.boot_req = 0;
writel(ownerx.u, CPC_BOOT_OWNERX(3));
} else {
ownerx.u = 0;
ownerx.s.boot_req = 1;
writel(ownerx.u, CPC_BOOT_OWNERX(3));
udelay(1);
do {
ownerx.u = readl(CPC_BOOT_OWNERX(3));
} while (ownerx.s.boot_wait);
}
}
int last_stage_init(void)
{
(void)smc_flsf_fw_booted();
return 0;
}
static int do_go_uboot(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
typedef void __noreturn (*uboot_entry_t)(ulong, void *);
uboot_entry_t entry;
ulong addr;
void *fdt;
if (argc < 2)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
fdt = board_fdt_blob_setup();
entry = (uboot_entry_t)addr;
flush_cache((ulong)addr, 1 << 20); /* 1MiB should be enough */
dcache_disable();
printf("## Starting U-Boot at %p (FDT at %p)...\n", entry, fdt);
entry(0, fdt);
return 0;
}
U_BOOT_CMD(go_uboot, 2, 0, do_go_uboot,
"Start U-Boot from RAM (pass FDT via x1 register)",
"");

58
board/Marvell/octeontx2/smc.c Normal file
View File

@@ -0,0 +1,58 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/arch/smc.h>
DECLARE_GLOBAL_DATA_PTR;
ssize_t smc_dram_size(unsigned int node)
{
struct pt_regs regs;
regs.regs[0] = OCTEONTX2_DRAM_SIZE;
regs.regs[1] = node;
smc_call(&regs);
return regs.regs[0];
}
ssize_t smc_disable_rvu_lfs(unsigned int node)
{
struct pt_regs regs;
regs.regs[0] = OCTEONTX2_DISABLE_RVU_LFS;
regs.regs[1] = node;
smc_call(&regs);
return regs.regs[0];
}
ssize_t smc_configure_ooo(unsigned int val)
{
struct pt_regs regs;
regs.regs[0] = OCTEONTX2_CONFIG_OOO;
regs.regs[1] = val;
smc_call(&regs);
return regs.regs[0];
}
ssize_t smc_flsf_fw_booted(void)
{
struct pt_regs regs;
regs.regs[0] = OCTEONTX2_FSAFE_PR_BOOT_SUCCESS;
smc_call(&regs);
return regs.regs[0];
}

49
board/Marvell/octeontx2/soc-utils.c Normal file
View File

@@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* https://spdx.org/licenses
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <asm/arch/soc.h>
#include <asm/arch/board.h>
#include <dm/util.h>
int read_platform(void)
{
int plat = PLATFORM_HW;
const char *model = fdt_get_board_model();
if (model && !strncmp(model, "ASIM-", 5))
plat = PLATFORM_ASIM;
if (model && !strncmp(model, "EMUL-", 5))
plat = PLATFORM_EMULATOR;
return plat;
}
static inline u64 read_midr(void)
{
u64 result;
asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
return result;
}
u8 read_partnum(void)
{
return ((read_midr() >> 4) & 0xFF);
}
const char *read_board_name(void)
{
return fdt_get_board_model();
}

47
board/renesas/rcar-common/common.c
View File

@@ -42,51 +42,4 @@ int dram_init_banksize(void)
return 0;
}
#if CONFIG_IS_ENABLED(OF_BOARD_SETUP) && CONFIG_IS_ENABLED(PCI)
int ft_board_setup(void *blob, struct bd_info *bd)
{
struct udevice *dev;
struct uclass *uc;
fdt_addr_t regs_addr;
int i, off, ret;
ret = uclass_get(UCLASS_PCI, &uc);
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
struct pci_controller hose = { 0 };
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
if (hose.region_count == MAX_PCI_REGIONS) {
printf("maximum number of regions parsed, aborting\n");
break;
}
if (bd->bi_dram[i].size) {
pci_set_region(&hose.regions[hose.region_count++],
bd->bi_dram[i].start,
bd->bi_dram[i].start,
bd->bi_dram[i].size,
PCI_REGION_MEM |
PCI_REGION_PREFETCH |
PCI_REGION_SYS_MEMORY);
}
}
regs_addr = devfdt_get_addr_index(dev, 0);
off = fdt_node_offset_by_compat_reg(blob,
"renesas,pcie-rcar-gen3", regs_addr);
if (off < 0) {
printf("Failed to find PCIe node@%llx\n", regs_addr);
return off;
}
fdt_pci_dma_ranges(blob, off, &hose);
}
return 0;
}
#endif
#endif

6
board/seco/Kconfig
View File

@@ -21,15 +21,15 @@ choice
config SECOMX6Q
bool "i.MX6Q"
select MX6Q
depends on MX6Q
config SECOMX6DL
bool "i.MX6DL"
select MX6DL
depends on MX6DL
config SECOMX6S
bool "i.MX6S"
select MX6S
depends on MX6S
endchoice

3
board/tbs/tbs2910/Kconfig
View File

@@ -9,9 +9,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "tbs2910"
config MX6Q
default y
config IMX_CONFIG
default "board/tbs/tbs2910/tbs2910.cfg"

53
board/technexion/pico-imx6ul/pico-imx6ul.c
View File

@@ -18,7 +18,6 @@
#include <asm/io.h>
#include <common.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/delay.h>
#include <linux/sizes.h>
#include <usb.h>
@@ -39,61 +38,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
static iomux_v3_cfg_t const fec_pads[] = {
MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
int board_eth_init(struct bd_info *bis)
{
setup_iomux_fec();
gpio_request(RMII_PHY_RESET, "enet_phy_reset");
gpio_direction_output(RMII_PHY_RESET, 0);
/*
* According to KSZ8081MNX-RNB manual:
* For warm reset, the reset (RST#) pin should be asserted low for a
* minimum of 500μs. The strap-in pin values are read and updated
* at the de-assertion of reset.
*/
udelay(500);
gpio_direction_output(RMII_PHY_RESET, 1);
/*
* According to KSZ8081MNX-RNB manual:
* After the de-assertion of reset, wait a minimum of 100μs before
* starting programming on the MIIM (MDC/MDIO) interface.
*/
udelay(100);
return fecmxc_initialize(bis);
}
static int setup_fec(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

6
board/tqc/tqma6/Kconfig
View File

@@ -18,19 +18,19 @@ choice
config TQMA6Q
bool "TQMa6Q / TQMa6D"
select MX6Q
depends on MX6Q
help
select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
config TQMA6DL
bool "TQMa6DL"
select MX6DL
depends on MX6DL
help
select TQMa6DL with i.MX6DL and 1GiB DRAM
config TQMA6S
bool "TQMa6S"
select MX6S
depends on MX6S
help
select TQMa6S with i.MX6S and 512 MiB DRAM

2
cmd/Kconfig
View File

@@ -860,7 +860,7 @@ config CMD_ARMFLASH
config CMD_ADC
bool "adc - Access Analog to Digital Converters info and data"
select ADC
select DM_REGULATOR
depends on DM_REGULATOR
help
Shows ADC device info and permit printing one-shot analog converted
data from a named Analog to Digital Converter.

4
cmd/mem.c
View File

@@ -30,10 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_MEMTEST_SCRATCH
#define CONFIG_SYS_MEMTEST_SCRATCH 0
#endif
/* Create a compile-time value */
#ifdef MEM_SUPPORT_64BIT_DATA
#define SUPPORT_64BIT_DATA 1

3
common/image.c
View File

@@ -694,6 +694,9 @@ phys_size_t env_get_bootm_size(void)
size = gd->bd->bi_memsize;
#endif
if (start + size > gd->ram_top)
size = gd->ram_top - start;
s = env_get("bootm_low");
if (s)
tmp = (phys_size_t)simple_strtoull(s, NULL, 16);

4
configs/am65x_evm_r5_usbdfu_defconfig
View File

@@ -4,6 +4,7 @@ CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
@@ -13,9 +14,9 @@ CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
@@ -49,7 +50,6 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y

10
configs/am65x_evm_r5_usbmsc_defconfig
View File

@@ -4,17 +4,19 @@ CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_USE_BOOTCOMMAND=y
@@ -47,7 +49,6 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -64,7 +65,6 @@ CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

3
configs/apalis_imx6_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6Q=y
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00908000
@@ -18,7 +19,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y

1
configs/aristainetos2_defconfig
View File

@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0xe000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xD0000
CONFIG_MX6DL=y
CONFIG_TARGET_ARISTAINETOS2=y
CONFIG_DM_GPIO=y
CONFIG_ENV_OFFSET_REDUND=0xE0000

1
configs/aristainetos2b_defconfig
View File

@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0xe000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xD0000
CONFIG_MX6DL=y
CONFIG_TARGET_ARISTAINETOS2B=y
CONFIG_DM_GPIO=y
CONFIG_ENV_OFFSET_REDUND=0xE0000

1
configs/aristainetos2bcsl_defconfig
View File

@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0xe000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xD0000
CONFIG_MX6DL=y
CONFIG_TARGET_ARISTAINETOS2BCSL=y
CONFIG_DM_GPIO=y
CONFIG_ENV_OFFSET_REDUND=0xE0000

1
configs/aristainetos2c_defconfig
View File

@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0xe000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xD0000
CONFIG_MX6DL=y
CONFIG_TARGET_ARISTAINETOS2C=y
CONFIG_DM_GPIO=y
CONFIG_ENV_OFFSET_REDUND=0xE0000

1
configs/brppt2_defconfig
View File

@@ -13,6 +13,7 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_BRPPT2=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068

1
configs/cgtqmx6eval_defconfig
View File

@@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_MX6QDL=y
CONFIG_TARGET_CGTQMX6EVAL=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC_SUPPORT=y

1
configs/cm_fx6_defconfig
View File

@@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_MX6QDL=y
CONFIG_TARGET_CM_FX6=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC_SUPPORT=y

3
configs/colibri-imx6ull_defconfig
View File

@@ -4,12 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x380000
CONFIG_MX6ULL=y
CONFIG_TARGET_COLIBRI_IMX6ULL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,MX6ULL,IMX_NAND"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,IMX_NAND"
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_CONSOLE_MUX is not set

3
configs/colibri_imx6_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6DL=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00908000
@@ -17,7 +18,7 @@ CONFIG_CMD_HDMIDETECT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y

1
configs/dh_imx6_defconfig
View File

@@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_MX6QDL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_DHCOMIMX6=y
CONFIG_DM_GPIO=y

3
configs/display5_defconfig
View File

@@ -10,6 +10,7 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x120000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_MX6Q=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_DISPLAY5=y
CONFIG_SYS_I2C_MXC_I2C1=y
@@ -31,7 +32,7 @@ CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y

3
configs/display5_factory_defconfig
View File

@@ -10,6 +10,7 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x120000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_MX6Q=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_DISPLAY5=y
CONFIG_SYS_I2C_MXC_I2C1=y
@@ -28,7 +29,7 @@ CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="echo SDP Display5 recovery"

1
configs/dms-ba16-1g_defconfig
View File

@@ -5,6 +5,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6Q=y
CONFIG_TARGET_ADVANTECH_DMS_BA16=y
CONFIG_SYS_DDR_1G=y
CONFIG_BOOTDELAY=1

1
configs/dms-ba16_defconfig
View File

@@ -5,6 +5,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6Q=y
CONFIG_TARGET_ADVANTECH_DMS_BA16=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

1
configs/ge_bx50v3_defconfig
View File

@@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6Q=y
CONFIG_TARGET_GE_BX50V3=y
CONFIG_DM_GPIO=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10

1
configs/gwventana_emmc_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xB1400
CONFIG_MX6QDL=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y

1
configs/gwventana_gw5904_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xB1400
CONFIG_MX6QDL=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y

1
configs/gwventana_nand_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x1000000
CONFIG_MX6QDL=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y

1
configs/imx6dl_icore_nand_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6dl_mamoj_defconfig
View File

@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6DL_MAMOJ=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_IMX_HAB=y

1
configs/imx6q_icore_nand_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6q_logic_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x100000
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6Q=y
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_MX6LOGICPD=y
CONFIG_SPL_TEXT_BASE=0x00908000

1
configs/imx6qdl_icore_mipi_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6qdl_icore_mmc_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6qdl_icore_nand_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6qdl_icore_rqs_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6ul_geam_mmc_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6ul_geam_nand_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

1
configs/imx6ul_isiot_emmc_defconfig
View File

@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL_SUPPORT=y

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