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sunxi: h3: Fix PLL1 setup to never use dividers

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Kernel would lower the divider on first CLK change and cause the
lock up.
This commit is contained in:
Ondrej Jirman
2016-12-20 11:25:12 +01:00
parent c8de2ee24b
commit 393dfccea1
1 changed files with 3 additions and 4 deletions
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7
arch/arm/mach-sunxi/clock_sun6i.c
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@@ -115,11 +115,10 @@ void clock_set_pll1(unsigned int clk)
int k = 1; int k = 1;
int m = 1; int m = 1;
if (clk > 1152000000) { if (clk >= 1368000000) {
k = 2;
} else if (clk > 768000000) {
k = 3; k = 3;
m = 2; } else if (clk >= 768000000) {
k = 2;
} }
/* Switch to 24MHz clock while changing PLL1 */ /* Switch to 24MHz clock while changing PLL1 */