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clk: uniphier: constify clock data arrays/structures

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Clarify these clock data are constant.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
2016-09-22 07:42:20 +09:00
parent c72f4d4c2e
commit 3524d47c79
3 changed files with 9 additions and 9 deletions
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6
drivers/clk/uniphier/clk-uniphier-core.c
View File

@@ -17,7 +17,7 @@
static int uniphier_clk_enable(struct clk *clk)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
struct uniphier_clk_gate_data *gate = priv->socdata->gate;
const struct uniphier_clk_gate_data *gate = priv->socdata->gate;
unsigned int nr_gate = priv->socdata->nr_gate;
void __iomem *reg;
u32 mask, data, tmp;
@@ -44,7 +44,7 @@ static int uniphier_clk_enable(struct clk *clk)
static ulong uniphier_clk_get_rate(struct clk *clk)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
unsigned int nr_rdata = priv->socdata->nr_rate;
void __iomem *reg;
u32 mask, data;
@@ -78,7 +78,7 @@ static ulong uniphier_clk_get_rate(struct clk *clk)
static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
unsigned int nr_rdata = priv->socdata->nr_rate;
void __iomem *reg;
u32 mask, data, tmp;

6
drivers/clk/uniphier/clk-uniphier-mio.c
View File

@@ -115,7 +115,7 @@
.data = 0x00020000, \
}
static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
UNIPHIER_MIO_CLK_GATE_SD(0, 0),
UNIPHIER_MIO_CLK_GATE_SD(1, 1),
UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */
@@ -126,13 +126,13 @@ static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */
};
static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
UNIPHIER_MIO_CLK_RATE_SD(0, 0),
UNIPHIER_MIO_CLK_RATE_SD(1, 1),
UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
};
static struct uniphier_clk_soc_data uniphier_mio_clk_data = {
static const struct uniphier_clk_soc_data uniphier_mio_clk_data = {
.gate = uniphier_mio_clk_gate,
.nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
.rate = uniphier_mio_clk_rate,

6
drivers/clk/uniphier/clk-uniphier.h
View File

@@ -27,9 +27,9 @@ struct uniphier_clk_rate_data {
};
struct uniphier_clk_soc_data {
struct uniphier_clk_gate_data *gate;
const struct uniphier_clk_gate_data *gate;
unsigned int nr_gate;
struct uniphier_clk_rate_data *rate;
const struct uniphier_clk_rate_data *rate;
unsigned int nr_rate;
};
@@ -48,7 +48,7 @@ struct uniphier_clk_soc_data {
*/
struct uniphier_clk_priv {
void __iomem *base;
struct uniphier_clk_soc_data *socdata;
const struct uniphier_clk_soc_data *socdata;
};
extern const struct clk_ops uniphier_clk_ops;