board: Add support for EBAZ4205

This is without the SD controller support, because I have a broken
uSD slot on my board. Until that's fixed, it needs to be disabled.

Signed-off-by: Ondrej Jirman <megi@xff.cz>

arch/arm/dts/Makefile

@@ -233,6 +233,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-cse-qspi-x2-single.dtb \
 	zynq-cse-qspi-x2-stacked.dtb \
 	zynq-dlc20-rev1.0.dtb \
+	zynq-ebaz-megi.dtb \
 	zynq-microzed.dtb \
 	zynq-minized.dtb \
 	zynq-picozed.dtb \

arch/arm/dts/zynq-ebaz-megi.dts

@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "EBAZ4205 board - megi config";
+	compatible = "megi,zynq-ebaz4205", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart1;
+		ethernet0 = &gem0;
+		mmc0 = &sdhci0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	ephy0_clk: ephy0-clk { 
+		#clock-cells = <0>; 
+		compatible = "fixed-clock"; 
+		clock-frequency = <25000000>; 
+		clock-output-names = "ephy0_clk"; 
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+	clocks = <&ephy0_clk>;
+	clock-names = "gem0_emio_clk";
+};
+
+&adc {
+	status = "disabled";
+};
+
+&gpio0 {
+	status = "disabled";
+};
+
+&smcc {
+	bootph-all;
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+	local-mac-address = [44 8F 17 36 1B A0];
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+		max-speed = <100>;
+	};
+};
+
+&sdhci0 {
+	bootph-all;
+	status = "okay";
+};
+
+&nfc0 {
+	status = "okay";
+	bootph-all;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nand@0 {
+		reg = <0>;
+/*
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "nand-fsbl-uboot";
+				reg = <0x0 0x1000000>;
+			};
+			partition@1000000 {
+				label = "nand-linux";
+				reg = <0x1000000 0x2000000>;
+			};
+			partition@3000000 {
+				label = "nand-rootfs";
+				reg = <0x3000000 0x200000>;
+			};
+		};
+*/
+	};
+};
+
+&uart1 {
+	bootph-all;
+	status = "okay";
+};

board/xilinx/zynq/zynq-ebaz-megi/ps7_init_gpl.h

@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2010-2020 <Xilinx Inc.>
+* 
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see <http://www.gnu.org/licenses/>
+* 
+* 
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  10000000
+#define SMC_FREQ  100000000
+#define ENET0_FREQ  25000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  100000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+

zynq.its

@@ -0,0 +1,47 @@
+/dts-v1/;
+/ {
+	description = "Firmware image with one or more FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		firmware-1 {
+			description = "U-Boot";
+			type = "firmware";
+			arch = "arm";
+			os = "u-boot";
+			compression = "none";
+			load = <0x4000000>;
+			entry = <0x4000000>;
+			data = /incbin/("u-boot-nodtb.bin");
+		};
+
+		fdt-1 {
+			description = "zynq-ebaz-megi";
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			data = /incbin/("arch/arm/dts/zynq-ebaz-megi.dtb");
+		};
+
+		fpga-1 {
+			description = "bitstream";
+			compatible = "u-boot,fpga-legacy";
+			type = "fpga";
+			arch = "arm";
+			load = <0x1000000>;
+			compression = "none";
+			data = /incbin/("fpga.bin");
+		};
+	};
+
+	configurations {
+		default = "conf-1";
+
+		conf-1 {
+			description = "zynq-ebaz-megi";
+			firmware = "firmware-1";
+			loadables = "fpga-1", "firmware-1";
+			fdt = "fdt-1";
+		};
+	};
+};