mirror of
https://github.com/linux-sunxi/meta-sunxi.git
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Merge pull request #366 from pblxptr/orange-pi-zero-2-poc
Introduce support for Orange PI Zero 2
This commit is contained in:
Marek Belisko
GitHub
commit
3fce491bba
9
conf/machine/include/sun50i-h616.inc
Normal file
9
conf/machine/include/sun50i-h616.inc
Normal file
@ -0,0 +1,9 @@
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require conf/machine/include/sunxi64.inc
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DEFAULTTUNE ?= "cortexa53-crypto"
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require conf/machine/include/arm/armv8a/tune-cortexa53.inc
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MACHINEOVERRIDES =. "sun50i:"
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SOC_FAMILY = "sun50i-h616"
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16
conf/machine/orange-pi-zero2.conf
Normal file
16
conf/machine/orange-pi-zero2.conf
Normal file
@ -0,0 +1,16 @@
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#@TYPE: Machine
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#@NAME: orange-pi-zero-2
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#@DESCRIPTION: Machine configuration for the orange-pi-zero-2, based on Allwinner H616 CPU
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require conf/machine/include/sun50i-h616.inc
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KERNEL_DEVICETREE = "allwinner/sun50i-h616-orangepi-zero2.dtb"
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UBOOT_MACHINE = "orangepi_zero2_defconfig"
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SPL_BINARY = "u-boot-sunxi-with-spl.bin"
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# as for now neither graphics nor audio is supported
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MACHINE_FEATURES:remove = "alsa x11"
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MACHINE_FEATURES:append = "bluetooth wifi"
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MACHINE_EXTRA_RRECOMMENDS = "uwe5622-firmware"
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@ -1,18 +1,24 @@
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DESCRIPTION = "ARM Trusted Firmware Allwinner"
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LICENSE = "BSD-3-Clause"
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LIC_FILES_CHKSUM = "file://license.md;md5=829bdeb34c1d9044f393d5a16c068371"
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LIC_FILES_CHKSUM:sun50i-h616 = "file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde"
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SRC_URI = "git://github.com/apritzel/arm-trusted-firmware;nobranch=1;protocol=https"
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SRC_URI = " \
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git://github.com/apritzel/arm-trusted-firmware;nobranch=1;protocol=https \
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file://0001-Use-same-type-as-in-declaration.patch \
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"
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SRCREV = "aa75c8da415158a94b82a430b2b40000778e851f"
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SRC_URI:append = " file://0001-Use-same-type-as-in-declaration.patch"
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SRC_URI:sun50i-h616 = "git://github.com/ARM-software/arm-trusted-firmware;nobranch=1;protocol=https"
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SRCREV:sun50i-h616 = "f04dfbb297f03d7f8d7f7c00ce8712e1a10295cf"
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S = "${WORKDIR}/git"
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B = "${WORKDIR}/build"
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COMPATIBLE_MACHINE = "(sun50i)"
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COMPATIBLE_MACHINE = "(sun50i|sun50i-h616)"
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PLATFORM:sun50i = "sun50iw1p1"
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PLATFORM:sun50i-h616 = "sun50i_h616"
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LDFLAGS[unexport] = "1"
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@ -0,0 +1,907 @@
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From 4de4213f698a5962f839f671e4dec247baa35d5b Mon Sep 17 00:00:00 2001
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From: Patryk Biel <patryk.biel.external@trumpf.com>
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Date: Wed, 25 Jan 2023 20:30:15 +0100
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Subject: [PATCH] Add device tree from master
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---
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arch/arm64/boot/dts/allwinner/Makefile | 1 +
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.../allwinner/sun50i-h616-orangepi-zero2.dts | 261 ++++++++
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.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 590 ++++++++++++++++++
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include/dt-bindings/clock/sun6i-rtc.h | 10 +
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4 files changed, 862 insertions(+)
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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create mode 100644 include/dt-bindings/clock/sun6i-rtc.h
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diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
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index a96d9d2d8..471822f5f 100644
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--- a/arch/arm64/boot/dts/allwinner/Makefile
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+++ b/arch/arm64/boot/dts/allwinner/Makefile
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@@ -37,3 +37,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
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+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
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\ No newline at end of file
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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new file mode 100644
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index 000000000..e92055145
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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@@ -0,0 +1,261 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+/*
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+ * Copyright (C) 2020 Arm Ltd.
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+ */
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+
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+/dts-v1/;
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+
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+#include "sun50i-h616.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/leds/common.h>
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+
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+/ {
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+ model = "OrangePi Zero2";
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+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
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+
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+ aliases {
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+ ethernet0 = &emac0;
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led-0 {
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+ function = LED_FUNCTION_POWER;
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+ color = <LED_COLOR_ID_RED>;
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+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
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+ default-state = "on";
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+ };
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+
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+ led-1 {
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+ function = LED_FUNCTION_STATUS;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
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+ };
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+ };
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+
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+ reg_vcc5v: vcc5v {
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+ /* board wide 5V supply directly from the USB-C socket */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-5v";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_vcc33_wifi: vcc33-wifi {
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+ /* Always on 3.3V regulator for WiFi and BT */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc33-wifi";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ vin-supply = <®_vcc5v>;
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+ };
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+
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+ reg_vcc_wifi_io: vcc-wifi-io {
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+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-wifi-io";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-always-on;
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+ vin-supply = <®_vcc33_wifi>;
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+ };
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+
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+ wifi_pwrseq: wifi-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rtc 1>;
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+ clock-names = "osc32k-out";
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+ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
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+ post-power-on-delay-ms = <200>;
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+ };
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+};
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+
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+&emac0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ext_rgmii_pins>;
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+ phy-mode = "rgmii";
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-supply = <®_dcdce>;
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+ allwinner,rx-delay-ps = <3100>;
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+ allwinner,tx-delay-ps = <700>;
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+ status = "okay";
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+};
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+
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+&mmc1 {
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+ vmmc-supply = <®_vcc33_wifi>;
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+ vqmmc-supply = <®_vcc_wifi_io>;
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+ mmc-pwrseq = <&wifi_pwrseq>;
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+ bus-width = <4>;
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+ non-removable;
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+ mmc-ddr-1_8v;
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+ status = "okay";
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+
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+ uwe-bsp {
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+ compatible = "unisoc,uwe_bsp";
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+ keep-power-on;
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+ data-irq;
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+ //adma-tx;
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+ adma-rx;
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+ //blksz-512;
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+ status = "okay";
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+ };
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+};
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+
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+&mdio0 {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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+
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+&mmc0 {
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+ vmmc-supply = <®_dcdce>;
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+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
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+ bus-width = <4>;
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+ status = "okay";
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+};
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+
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+&r_rsb {
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+ status = "okay";
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+
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+ axp305: pmic@745 {
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+ compatible = "x-powers,axp305", "x-powers,axp805",
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+ "x-powers,axp806";
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ reg = <0x745>;
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+
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+ x-powers,self-working-mode;
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+ vina-supply = <®_vcc5v>;
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+ vinb-supply = <®_vcc5v>;
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+ vinc-supply = <®_vcc5v>;
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+ vind-supply = <®_vcc5v>;
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+ vine-supply = <®_vcc5v>;
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+ aldoin-supply = <®_vcc5v>;
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+ bldoin-supply = <®_vcc5v>;
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+ cldoin-supply = <®_vcc5v>;
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+
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+ regulators {
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+ reg_aldo1: aldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc-sys";
|
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+ };
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+
|
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+ reg_aldo2: aldo2 { /* 3.3V on headers */
|
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <3300000>;
|
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+ regulator-max-microvolt = <3300000>;
|
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+ regulator-name = "vcc3v3-ext";
|
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+ };
|
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+
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+ reg_aldo3: aldo3 { /* 3.3V on headers */
|
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc3v3-ext2";
|
||||
+ };
|
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+
|
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+ reg_bldo1: bldo1 {
|
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+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc1v8";
|
||||
+ };
|
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+
|
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+ bldo2 {
|
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+ /* unused */
|
||||
+ };
|
||||
+
|
||||
+ bldo3 {
|
||||
+ /* unused */
|
||||
+ };
|
||||
+
|
||||
+ bldo4 {
|
||||
+ /* unused */
|
||||
+ };
|
||||
+
|
||||
+ cldo1 {
|
||||
+ /* reserved */
|
||||
+ };
|
||||
+
|
||||
+ cldo2 {
|
||||
+ /* unused */
|
||||
+ };
|
||||
+
|
||||
+ cldo3 {
|
||||
+ /* unused */
|
||||
+ };
|
||||
+
|
||||
+ reg_dcdca: dcdca {
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <810000>;
|
||||
+ regulator-max-microvolt = <1100000>;
|
||||
+ regulator-name = "vdd-cpu";
|
||||
+ };
|
||||
+
|
||||
+ reg_dcdcc: dcdcc {
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <810000>;
|
||||
+ regulator-max-microvolt = <990000>;
|
||||
+ regulator-name = "vdd-gpu-sys";
|
||||
+ };
|
||||
+
|
||||
+ reg_dcdcd: dcdcd {
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-name = "vdd-dram";
|
||||
+ };
|
||||
+
|
||||
+ reg_dcdce: dcdce {
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc-eth-mmc";
|
||||
+ };
|
||||
+
|
||||
+ sw {
|
||||
+ /* unused */
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pio {
|
||||
+ vcc-pc-supply = <®_aldo1>;
|
||||
+ vcc-pf-supply = <®_aldo1>;
|
||||
+ vcc-pg-supply = <®_bldo1>;
|
||||
+ vcc-ph-supply = <®_aldo1>;
|
||||
+ vcc-pi-supply = <®_aldo1>;
|
||||
+};
|
||||
+
|
||||
+&spi0 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
|
||||
+
|
||||
+ flash@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <40000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_ph_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
new file mode 100644
|
||||
index 000000000..ab344ea8a
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
@@ -0,0 +1,590 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+// Copyright (C) 2020 Arm Ltd.
|
||||
+// based on the H6 dtsi, which is:
|
||||
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+#include <dt-bindings/clock/sun50i-h616-ccu.h>
|
||||
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
|
||||
+#include <dt-bindings/clock/sun6i-rtc.h>
|
||||
+#include <dt-bindings/reset/sun50i-h616-ccu.h>
|
||||
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
|
||||
+
|
||||
+/ {
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ cpu0: cpu@0 {
|
||||
+ compatible = "arm,cortex-a53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0>;
|
||||
+ enable-method = "psci";
|
||||
+ clocks = <&ccu CLK_CPUX>;
|
||||
+ };
|
||||
+
|
||||
+ cpu1: cpu@1 {
|
||||
+ compatible = "arm,cortex-a53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <1>;
|
||||
+ enable-method = "psci";
|
||||
+ clocks = <&ccu CLK_CPUX>;
|
||||
+ };
|
||||
+
|
||||
+ cpu2: cpu@2 {
|
||||
+ compatible = "arm,cortex-a53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <2>;
|
||||
+ enable-method = "psci";
|
||||
+ clocks = <&ccu CLK_CPUX>;
|
||||
+ };
|
||||
+
|
||||
+ cpu3: cpu@3 {
|
||||
+ compatible = "arm,cortex-a53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <3>;
|
||||
+ enable-method = "psci";
|
||||
+ clocks = <&ccu CLK_CPUX>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+
|
||||
+ /*
|
||||
+ * 256 KiB reserved for Trusted Firmware-A (BL31).
|
||||
+ * This is added by BL31 itself, but some bootloaders fail
|
||||
+ * to propagate this into the DTB handed to kernels.
|
||||
+ */
|
||||
+ secmon@40000000 {
|
||||
+ reg = <0x0 0x40000000 0x0 0x40000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ osc24M: osc24M-clk {
|
||||
+ #clock-cells = <0>;
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <24000000>;
|
||||
+ clock-output-names = "osc24M";
|
||||
+ };
|
||||
+
|
||||
+ pmu {
|
||||
+ compatible = "arm,cortex-a53-pmu";
|
||||
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
+ };
|
||||
+
|
||||
+ psci {
|
||||
+ compatible = "arm,psci-0.2";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ arm,no-tick-in-suspend;
|
||||
+ interrupts = <GIC_PPI 13
|
||||
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
+ <GIC_PPI 14
|
||||
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
+ <GIC_PPI 11
|
||||
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
+ <GIC_PPI 10
|
||||
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ };
|
||||
+
|
||||
+ soc {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0x0 0x40000000>;
|
||||
+
|
||||
+ syscon: syscon@3000000 {
|
||||
+ compatible = "allwinner,sun50i-h616-system-control";
|
||||
+ reg = <0x03000000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ sram_c: sram@28000 {
|
||||
+ compatible = "mmio-sram";
|
||||
+ reg = <0x00028000 0x30000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0 0x00028000 0x30000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ccu: clock@3001000 {
|
||||
+ compatible = "allwinner,sun50i-h616-ccu";
|
||||
+ reg = <0x03001000 0x1000>;
|
||||
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
|
||||
+ clock-names = "hosc", "losc", "iosc";
|
||||
+ #clock-cells = <1>;
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ watchdog: watchdog@30090a0 {
|
||||
+ compatible = "allwinner,sun50i-h616-wdt",
|
||||
+ "allwinner,sun6i-a31-wdt";
|
||||
+ reg = <0x030090a0 0x20>;
|
||||
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&osc24M>;
|
||||
+ };
|
||||
+
|
||||
+ pio: pinctrl@300b000 {
|
||||
+ compatible = "allwinner,sun50i-h616-pinctrl";
|
||||
+ reg = <0x0300b000 0x400>;
|
||||
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
|
||||
+ clock-names = "apb", "hosc", "losc";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <3>;
|
||||
+
|
||||
+ ext_rgmii_pins: rgmii-pins {
|
||||
+ pins = "PI0", "PI1", "PI2", "PI3", "PI4",
|
||||
+ "PI5", "PI7", "PI8", "PI9", "PI10",
|
||||
+ "PI11", "PI12", "PI13", "PI14", "PI15",
|
||||
+ "PI16";
|
||||
+ function = "emac0";
|
||||
+ drive-strength = <40>;
|
||||
+ };
|
||||
+
|
||||
+ i2c0_pins: i2c0-pins {
|
||||
+ pins = "PI6", "PI7";
|
||||
+ function = "i2c0";
|
||||
+ };
|
||||
+
|
||||
+ i2c3_ph_pins: i2c3-ph-pins {
|
||||
+ pins = "PH4", "PH5";
|
||||
+ function = "i2c3";
|
||||
+ };
|
||||
+
|
||||
+ ir_rx_pin: ir-rx-pin {
|
||||
+ pins = "PH10";
|
||||
+ function = "ir_rx";
|
||||
+ };
|
||||
+
|
||||
+ mmc0_pins: mmc0-pins {
|
||||
+ pins = "PF0", "PF1", "PF2", "PF3",
|
||||
+ "PF4", "PF5";
|
||||
+ function = "mmc0";
|
||||
+ drive-strength = <30>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ mmc1_pins: mmc1-pins {
|
||||
+ pins = "PG0", "PG1", "PG2", "PG3",
|
||||
+ "PG4", "PG5";
|
||||
+ function = "mmc1";
|
||||
+ drive-strength = <30>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ mmc2_pins: mmc2-pins {
|
||||
+ pins = "PC0", "PC1", "PC5", "PC6",
|
||||
+ "PC8", "PC9", "PC10", "PC11",
|
||||
+ "PC13", "PC14", "PC15", "PC16";
|
||||
+ function = "mmc2";
|
||||
+ drive-strength = <30>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ spi0_pins: spi0-pins {
|
||||
+ pins = "PC0", "PC2", "PC4";
|
||||
+ function = "spi0";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ spi0_cs0_pin: spi0-cs0-pin {
|
||||
+ pins = "PC3";
|
||||
+ function = "spi0";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ spi1_pins: spi1-pins {
|
||||
+ pins = "PH6", "PH7", "PH8";
|
||||
+ function = "spi1";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ spi1_cs0_pin: spi1-cs0-pin {
|
||||
+ pins = "PH5";
|
||||
+ function = "spi1";
|
||||
+ };
|
||||
+
|
||||
+ uart0_ph_pins: uart0-ph-pins {
|
||||
+ pins = "PH0", "PH1";
|
||||
+ function = "uart0";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ uart1_pins: uart1-pins {
|
||||
+ pins = "PG6", "PG7";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
|
||||
+ pins = "PG8", "PG9";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gic: interrupt-controller@3021000 {
|
||||
+ compatible = "arm,gic-400";
|
||||
+ reg = <0x03021000 0x1000>,
|
||||
+ <0x03022000 0x2000>,
|
||||
+ <0x03024000 0x2000>,
|
||||
+ <0x03026000 0x2000>;
|
||||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <3>;
|
||||
+ };
|
||||
+
|
||||
+ mmc0: mmc@4020000 {
|
||||
+ compatible = "allwinner,sun50i-h616-mmc",
|
||||
+ "allwinner,sun50i-a100-mmc";
|
||||
+ reg = <0x04020000 0x1000>;
|
||||
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
||||
+ clock-names = "ahb", "mmc";
|
||||
+ resets = <&ccu RST_BUS_MMC0>;
|
||||
+ reset-names = "ahb";
|
||||
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&mmc0_pins>;
|
||||
+ status = "disabled";
|
||||
+ max-frequency = <150000000>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-mmc-highspeed;
|
||||
+ mmc-ddr-3_3v;
|
||||
+ cap-sdio-irq;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ mmc1: mmc@4021000 {
|
||||
+ compatible = "allwinner,sun50i-h616-mmc",
|
||||
+ "allwinner,sun50i-a100-mmc";
|
||||
+ reg = <0x04021000 0x1000>;
|
||||
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
||||
+ clock-names = "ahb", "mmc";
|
||||
+ resets = <&ccu RST_BUS_MMC1>;
|
||||
+ reset-names = "ahb";
|
||||
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&mmc1_pins>;
|
||||
+ status = "disabled";
|
||||
+ max-frequency = <150000000>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-mmc-highspeed;
|
||||
+ mmc-ddr-3_3v;
|
||||
+ cap-sdio-irq;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ mmc2: mmc@4022000 {
|
||||
+ compatible = "allwinner,sun50i-h616-emmc",
|
||||
+ "allwinner,sun50i-a100-emmc";
|
||||
+ reg = <0x04022000 0x1000>;
|
||||
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
||||
+ clock-names = "ahb", "mmc";
|
||||
+ resets = <&ccu RST_BUS_MMC2>;
|
||||
+ reset-names = "ahb";
|
||||
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&mmc2_pins>;
|
||||
+ status = "disabled";
|
||||
+ max-frequency = <150000000>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-mmc-highspeed;
|
||||
+ mmc-ddr-3_3v;
|
||||
+ cap-sdio-irq;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ uart0: serial@5000000 {
|
||||
+ compatible = "snps,dw-apb-uart";
|
||||
+ reg = <0x05000000 0x400>;
|
||||
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ reg-io-width = <4>;
|
||||
+ clocks = <&ccu CLK_BUS_UART0>;
|
||||
+ resets = <&ccu RST_BUS_UART0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uart1: serial@5000400 {
|
||||
+ compatible = "snps,dw-apb-uart";
|
||||
+ reg = <0x05000400 0x400>;
|
||||
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ reg-io-width = <4>;
|
||||
+ clocks = <&ccu CLK_BUS_UART1>;
|
||||
+ resets = <&ccu RST_BUS_UART1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uart2: serial@5000800 {
|
||||
+ compatible = "snps,dw-apb-uart";
|
||||
+ reg = <0x05000800 0x400>;
|
||||
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ reg-io-width = <4>;
|
||||
+ clocks = <&ccu CLK_BUS_UART2>;
|
||||
+ resets = <&ccu RST_BUS_UART2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uart3: serial@5000c00 {
|
||||
+ compatible = "snps,dw-apb-uart";
|
||||
+ reg = <0x05000c00 0x400>;
|
||||
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ reg-io-width = <4>;
|
||||
+ clocks = <&ccu CLK_BUS_UART3>;
|
||||
+ resets = <&ccu RST_BUS_UART3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uart4: serial@5001000 {
|
||||
+ compatible = "snps,dw-apb-uart";
|
||||
+ reg = <0x05001000 0x400>;
|
||||
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ reg-io-width = <4>;
|
||||
+ clocks = <&ccu CLK_BUS_UART4>;
|
||||
+ resets = <&ccu RST_BUS_UART4>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uart5: serial@5001400 {
|
||||
+ compatible = "snps,dw-apb-uart";
|
||||
+ reg = <0x05001400 0x400>;
|
||||
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ reg-io-width = <4>;
|
||||
+ clocks = <&ccu CLK_BUS_UART5>;
|
||||
+ resets = <&ccu RST_BUS_UART5>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ i2c0: i2c@5002000 {
|
||||
+ compatible = "allwinner,sun50i-h616-i2c",
|
||||
+ "allwinner,sun8i-v536-i2c",
|
||||
+ "allwinner,sun6i-a31-i2c";
|
||||
+ reg = <0x05002000 0x400>;
|
||||
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_I2C0>;
|
||||
+ resets = <&ccu RST_BUS_I2C0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2c0_pins>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ i2c1: i2c@5002400 {
|
||||
+ compatible = "allwinner,sun50i-h616-i2c",
|
||||
+ "allwinner,sun8i-v536-i2c",
|
||||
+ "allwinner,sun6i-a31-i2c";
|
||||
+ reg = <0x05002400 0x400>;
|
||||
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_I2C1>;
|
||||
+ resets = <&ccu RST_BUS_I2C1>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ i2c2: i2c@5002800 {
|
||||
+ compatible = "allwinner,sun50i-h616-i2c",
|
||||
+ "allwinner,sun8i-v536-i2c",
|
||||
+ "allwinner,sun6i-a31-i2c";
|
||||
+ reg = <0x05002800 0x400>;
|
||||
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_I2C2>;
|
||||
+ resets = <&ccu RST_BUS_I2C2>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ i2c3: i2c@5002c00 {
|
||||
+ compatible = "allwinner,sun50i-h616-i2c",
|
||||
+ "allwinner,sun8i-v536-i2c",
|
||||
+ "allwinner,sun6i-a31-i2c";
|
||||
+ reg = <0x05002c00 0x400>;
|
||||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_I2C3>;
|
||||
+ resets = <&ccu RST_BUS_I2C3>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ i2c4: i2c@5003000 {
|
||||
+ compatible = "allwinner,sun50i-h616-i2c",
|
||||
+ "allwinner,sun8i-v536-i2c",
|
||||
+ "allwinner,sun6i-a31-i2c";
|
||||
+ reg = <0x05003000 0x400>;
|
||||
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_I2C4>;
|
||||
+ resets = <&ccu RST_BUS_I2C4>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ spi0: spi@5010000 {
|
||||
+ compatible = "allwinner,sun50i-h616-spi",
|
||||
+ "allwinner,sun8i-h3-spi";
|
||||
+ reg = <0x05010000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
||||
+ clock-names = "ahb", "mod";
|
||||
+ resets = <&ccu RST_BUS_SPI0>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ spi1: spi@5011000 {
|
||||
+ compatible = "allwinner,sun50i-h616-spi",
|
||||
+ "allwinner,sun8i-h3-spi";
|
||||
+ reg = <0x05011000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
||||
+ clock-names = "ahb", "mod";
|
||||
+ resets = <&ccu RST_BUS_SPI1>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ emac0: ethernet@5020000 {
|
||||
+ compatible = "allwinner,sun50i-h616-emac0",
|
||||
+ "allwinner,sun50i-a64-emac";
|
||||
+ reg = <0x05020000 0x10000>;
|
||||
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+ clocks = <&ccu CLK_BUS_EMAC0>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+ resets = <&ccu RST_BUS_EMAC0>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+ syscon = <&syscon>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ mdio0: mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rtc: rtc@7000000 {
|
||||
+ compatible = "allwinner,sun50i-h616-rtc",
|
||||
+ "allwinner,sun50i-h6-rtc";
|
||||
+ reg = <0x07000000 0x400>;
|
||||
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clock-output-names = "osc32k", "osc32k-out", "iosc";
|
||||
+ #clock-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ r_ccu: clock@7010000 {
|
||||
+ compatible = "allwinner,sun50i-h616-r-ccu";
|
||||
+ reg = <0x07010000 0x210>;
|
||||
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
|
||||
+ <&ccu CLK_PLL_PERIPH0>;
|
||||
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
|
||||
+ #clock-cells = <1>;
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ r_pio: pinctrl@7022000 {
|
||||
+ compatible = "allwinner,sun50i-h616-r-pinctrl";
|
||||
+ reg = <0x07022000 0x400>;
|
||||
+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
|
||||
+ <&rtc CLK_OSC32K>;
|
||||
+ clock-names = "apb", "hosc", "losc";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <3>;
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ r_i2c_pins: r-i2c-pins {
|
||||
+ pins = "PL0", "PL1";
|
||||
+ function = "s_i2c";
|
||||
+ };
|
||||
+
|
||||
+ r_rsb_pins: r-rsb-pins {
|
||||
+ pins = "PL0", "PL1";
|
||||
+ function = "s_rsb";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ir: ir@7040000 {
|
||||
+ compatible = "allwinner,sun50i-h616-ir",
|
||||
+ "allwinner,sun6i-a31-ir";
|
||||
+ reg = <0x07040000 0x400>;
|
||||
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&r_ccu CLK_R_APB1_IR>,
|
||||
+ <&r_ccu CLK_IR>;
|
||||
+ clock-names = "apb", "ir";
|
||||
+ resets = <&r_ccu RST_R_APB1_IR>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&ir_rx_pin>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ r_i2c: i2c@7081400 {
|
||||
+ compatible = "allwinner,sun50i-h616-i2c",
|
||||
+ "allwinner,sun8i-v536-i2c",
|
||||
+ "allwinner,sun6i-a31-i2c";
|
||||
+ reg = <0x07081400 0x400>;
|
||||
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&r_ccu CLK_R_APB2_I2C>;
|
||||
+ resets = <&r_ccu RST_R_APB2_I2C>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ r_rsb: rsb@7083000 {
|
||||
+ compatible = "allwinner,sun50i-h616-rsb",
|
||||
+ "allwinner,sun8i-a23-rsb";
|
||||
+ reg = <0x07083000 0x400>;
|
||||
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&r_ccu CLK_R_APB2_RSB>;
|
||||
+ clock-frequency = <3000000>;
|
||||
+ resets = <&r_ccu RST_R_APB2_RSB>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&r_rsb_pins>;
|
||||
+ status = "disabled";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
|
||||
new file mode 100644
|
||||
index 000000000..c845493e4
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/clock/sun6i-rtc.h
|
||||
@@ -0,0 +1,10 @@
|
||||
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
+
|
||||
+#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
|
||||
+#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
|
||||
+
|
||||
+#define CLK_OSC32K 0
|
||||
+#define CLK_OSC32K_FANOUT 1
|
||||
+#define CLK_IOSC 2
|
||||
+
|
||||
+#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */
|
||||
--
|
||||
2.34.1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,60 @@
|
||||
From 452a691a83df1aab77cec33203cb04a817817a05 Mon Sep 17 00:00:00 2001
|
||||
From: The-going <48602507+The-going@users.noreply.github.com>
|
||||
Date: Thu, 5 May 2022 22:55:13 +0300
|
||||
Subject: [PATCH] drv: nvmem: sunxi_sid: Add sunxi_get_soc_chipid,
|
||||
sunxi_get_serial
|
||||
|
||||
---
|
||||
drivers/nvmem/sunxi_sid.c | 28 ++++++++++++++++++++++++++++
|
||||
1 file changed, 28 insertions(+)
|
||||
|
||||
diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
|
||||
index 37a6abb0e..c81fac63d 100644
|
||||
--- a/drivers/nvmem/sunxi_sid.c
|
||||
+++ b/drivers/nvmem/sunxi_sid.c
|
||||
@@ -37,6 +37,25 @@ struct sunxi_sid {
|
||||
u32 value_offset;
|
||||
};
|
||||
|
||||
+static unsigned int sunxi_soc_chipid[4];
|
||||
+static unsigned int sunxi_serial[4];
|
||||
+
|
||||
+int sunxi_get_soc_chipid(unsigned char *chipid)
|
||||
+{
|
||||
+ memcpy(chipid, sunxi_soc_chipid, 16);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+EXPORT_SYMBOL(sunxi_get_soc_chipid);
|
||||
+
|
||||
+int sunxi_get_serial(unsigned char *serial)
|
||||
+{
|
||||
+ memcpy(serial, sunxi_serial, 16);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+EXPORT_SYMBOL(sunxi_get_serial);
|
||||
+
|
||||
static int sunxi_sid_read(void *context, unsigned int offset,
|
||||
void *val, size_t bytes)
|
||||
{
|
||||
@@ -167,6 +186,15 @@ static int sunxi_sid_probe(struct platform_device *pdev)
|
||||
|
||||
platform_set_drvdata(pdev, nvmem);
|
||||
|
||||
+ nvmem_cfg->reg_read(sid, 0, &sunxi_soc_chipid[0], sizeof(int));
|
||||
+ nvmem_cfg->reg_read(sid, 4, &sunxi_soc_chipid[1], sizeof(int));
|
||||
+ nvmem_cfg->reg_read(sid, 8, &sunxi_soc_chipid[2], sizeof(int));
|
||||
+ nvmem_cfg->reg_read(sid, 12, &sunxi_soc_chipid[3], sizeof(int));
|
||||
+
|
||||
+ sunxi_serial[0] = sunxi_soc_chipid[3];
|
||||
+ sunxi_serial[1] = sunxi_soc_chipid[2];
|
||||
+ sunxi_serial[2] = (sunxi_soc_chipid[1] >> 16) & 0x0ffff;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--
|
||||
2.35.3
|
||||
|
||||
|
||||
@ -0,0 +1,27 @@
|
||||
From 9a7776b44588c24d04ffff63194d8a137624f8ac Mon Sep 17 00:00:00 2001
|
||||
From: Patryk Biel <patryk.biel.external@trumpf.com>
|
||||
Date: Thu, 26 Jan 2023 09:50:42 +0100
|
||||
Subject: [PATCH] Add sunxi-info device tree node
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
index ab344ea8a..d0b95d43a 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
@@ -586,5 +586,10 @@ r_rsb: rsb@7083000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
+
|
||||
+ sunxi-info {
|
||||
+ compatible = "allwinner,sun50i-h616-sys-info";
|
||||
+ status = "okay";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--
|
||||
2.34.1
|
||||
|
||||
@ -0,0 +1,32 @@
|
||||
From 706dc6ed092e4a1b9d84893cb4186fbd354bb1c8 Mon Sep 17 00:00:00 2001
|
||||
From: Patryk Biel <patryk.biel.external@trumpf.com>
|
||||
Date: Thu, 26 Jan 2023 09:51:22 +0100
|
||||
Subject: [PATCH] Add addr_mgt device tree node
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
index d0b95d43a..15f45a3f9 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
|
||||
@@ -591,5 +591,15 @@ sunxi-info {
|
||||
compatible = "allwinner,sun50i-h616-sys-info";
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+ addr_mgt {
|
||||
+ compatible = "allwinner,sunxi-addr_mgt";
|
||||
+ type_addr_wifi = <0x00>;
|
||||
+ type_addr_bt = <0x00>;
|
||||
+ type_addr_eth = <0x00>;
|
||||
+ status = "okay";
|
||||
+ linux,phandle = <0x179>;
|
||||
+ phandle = <0x179>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--
|
||||
2.34.1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,613 @@
|
||||
From 29cfa9437eaa2ff862ab0f06852383b181b60743 Mon Sep 17 00:00:00 2001
|
||||
From: afaulkner420 <afaulkner420@gmail.com>
|
||||
Date: Fri, 25 Mar 2022 20:18:18 +0000
|
||||
Subject: [PATCH 04/11] Add sunxi-addr driver - Used to fix uwe5622 bluetooth
|
||||
MAC addresses
|
||||
|
||||
---
|
||||
drivers/misc/Kconfig | 1 +
|
||||
drivers/misc/Makefile | 1 +
|
||||
drivers/misc/sunxi-addr/Kconfig | 6 +
|
||||
drivers/misc/sunxi-addr/Makefile | 5 +
|
||||
drivers/misc/sunxi-addr/sha256.c | 178 +++++++++++++
|
||||
drivers/misc/sunxi-addr/sunxi-addr.c | 358 +++++++++++++++++++++++++++
|
||||
6 files changed, 549 insertions(+)
|
||||
create mode 100644 drivers/misc/sunxi-addr/Kconfig
|
||||
create mode 100644 drivers/misc/sunxi-addr/Makefile
|
||||
create mode 100644 drivers/misc/sunxi-addr/sha256.c
|
||||
create mode 100644 drivers/misc/sunxi-addr/sunxi-addr.c
|
||||
|
||||
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
|
||||
index 24cb809ae..52843042f 100644
|
||||
--- a/drivers/misc/Kconfig
|
||||
+++ b/drivers/misc/Kconfig
|
||||
@@ -494,4 +494,5 @@ source "drivers/misc/cardreader/Kconfig"
|
||||
source "drivers/misc/habanalabs/Kconfig"
|
||||
source "drivers/misc/uacce/Kconfig"
|
||||
source "drivers/misc/pvpanic/Kconfig"
|
||||
+source "drivers/misc/sunxi-addr/Kconfig"
|
||||
endmenu
|
||||
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
|
||||
index f3eaa577a..0f9280509 100644
|
||||
--- a/drivers/misc/Makefile
|
||||
+++ b/drivers/misc/Makefile
|
||||
@@ -60,3 +60,4 @@ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
|
||||
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
|
||||
obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o
|
||||
obj-$(CONFIG_MODEM_POWER) += modem-power.o
|
||||
+obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi-addr/
|
||||
\ No newline at end of file
|
||||
diff --git a/drivers/misc/sunxi-addr/Kconfig b/drivers/misc/sunxi-addr/Kconfig
|
||||
new file mode 100644
|
||||
index 000000000..801dd2c02
|
||||
--- /dev/null
|
||||
+++ b/drivers/misc/sunxi-addr/Kconfig
|
||||
@@ -0,0 +1,6 @@
|
||||
+config SUNXI_ADDR_MGT
|
||||
+ tristate "Allwinner Network MAC Addess Manager"
|
||||
+ depends on BT || ETHERNET || WLAN
|
||||
+ depends on NVMEM_SUNXI_SID
|
||||
+ help
|
||||
+ allwinner network mac address management
|
||||
diff --git a/drivers/misc/sunxi-addr/Makefile b/drivers/misc/sunxi-addr/Makefile
|
||||
new file mode 100644
|
||||
index 000000000..f01fd4783
|
||||
--- /dev/null
|
||||
+++ b/drivers/misc/sunxi-addr/Makefile
|
||||
@@ -0,0 +1,5 @@
|
||||
+#
|
||||
+# Makefile for wifi mac addr manager drivers
|
||||
+#
|
||||
+sunxi_addr-objs := sunxi-addr.o sha256.o
|
||||
+obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi_addr.o
|
||||
diff --git a/drivers/misc/sunxi-addr/sha256.c b/drivers/misc/sunxi-addr/sha256.c
|
||||
new file mode 100644
|
||||
index 000000000..78825810c
|
||||
--- /dev/null
|
||||
+++ b/drivers/misc/sunxi-addr/sha256.c
|
||||
@@ -0,0 +1,178 @@
|
||||
+/*
|
||||
+ * Local implement of sha256.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 Allwinner.
|
||||
+ *
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without any
|
||||
+ * warranty of any kind, whether express or implied.
|
||||
+ */
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/string.h>
|
||||
+
|
||||
+/****************************** MACROS ******************************/
|
||||
+#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (32 - (b))))
|
||||
+#define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z)))
|
||||
+#define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
|
||||
+#define EP0(x) (ROTRIGHT(x, 2) ^ ROTRIGHT(x, 13) ^ ROTRIGHT(x, 22))
|
||||
+#define EP1(x) (ROTRIGHT(x, 6) ^ ROTRIGHT(x, 11) ^ ROTRIGHT(x, 25))
|
||||
+#define SIG0(x) (ROTRIGHT(x, 7) ^ ROTRIGHT(x, 18) ^ ((x) >> 3))
|
||||
+#define SIG1(x) (ROTRIGHT(x, 17) ^ ROTRIGHT(x, 19) ^ ((x) >> 10))
|
||||
+
|
||||
+/**************************** VARIABLES *****************************/
|
||||
+static const uint32_t k[64] = {
|
||||
+ 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
|
||||
+ 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
|
||||
+ 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
|
||||
+ 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
|
||||
+ 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
|
||||
+ 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
|
||||
+ 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
|
||||
+ 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
|
||||
+ 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
|
||||
+ 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
|
||||
+ 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
|
||||
+ 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
|
||||
+ 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
|
||||
+ 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
|
||||
+ 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
|
||||
+ 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
|
||||
+};
|
||||
+
|
||||
+struct sha256_ctx {
|
||||
+ uint8_t data[64]; /* current 512-bit chunk of message data, just like a buffer */
|
||||
+ uint32_t datalen; /* sign the data length of current chunk */
|
||||
+ uint64_t bitlen; /* the bit length of the total message */
|
||||
+ uint32_t state[8]; /* store the middle state of hash abstract */
|
||||
+};
|
||||
+
|
||||
+/*********************** FUNCTION DEFINITIONS ***********************/
|
||||
+static void sha256_transform(struct sha256_ctx *ctx, const uint8_t *data)
|
||||
+{
|
||||
+ uint32_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[64];
|
||||
+
|
||||
+ /* initialization */
|
||||
+ for (i = 0, j = 0; i < 16; ++i, j += 4)
|
||||
+ m[i] = (data[j] << 24) | (data[j + 1] << 16) |
|
||||
+ (data[j + 2] << 8) | (data[j + 3]);
|
||||
+ for ( ; i < 64; ++i)
|
||||
+ m[i] = SIG1(m[i - 2]) + m[i - 7] + SIG0(m[i - 15]) + m[i - 16];
|
||||
+
|
||||
+ a = ctx->state[0];
|
||||
+ b = ctx->state[1];
|
||||
+ c = ctx->state[2];
|
||||
+ d = ctx->state[3];
|
||||
+ e = ctx->state[4];
|
||||
+ f = ctx->state[5];
|
||||
+ g = ctx->state[6];
|
||||
+ h = ctx->state[7];
|
||||
+
|
||||
+ for (i = 0; i < 64; ++i) {
|
||||
+ t1 = h + EP1(e) + CH(e, f, g) + k[i] + m[i];
|
||||
+ t2 = EP0(a) + MAJ(a, b, c);
|
||||
+ h = g;
|
||||
+ g = f;
|
||||
+ f = e;
|
||||
+ e = d + t1;
|
||||
+ d = c;
|
||||
+ c = b;
|
||||
+ b = a;
|
||||
+ a = t1 + t2;
|
||||
+ }
|
||||
+
|
||||
+ ctx->state[0] += a;
|
||||
+ ctx->state[1] += b;
|
||||
+ ctx->state[2] += c;
|
||||
+ ctx->state[3] += d;
|
||||
+ ctx->state[4] += e;
|
||||
+ ctx->state[5] += f;
|
||||
+ ctx->state[6] += g;
|
||||
+ ctx->state[7] += h;
|
||||
+}
|
||||
+
|
||||
+static void sha256_init(struct sha256_ctx *ctx)
|
||||
+{
|
||||
+ ctx->datalen = 0;
|
||||
+ ctx->bitlen = 0;
|
||||
+ ctx->state[0] = 0x6a09e667;
|
||||
+ ctx->state[1] = 0xbb67ae85;
|
||||
+ ctx->state[2] = 0x3c6ef372;
|
||||
+ ctx->state[3] = 0xa54ff53a;
|
||||
+ ctx->state[4] = 0x510e527f;
|
||||
+ ctx->state[5] = 0x9b05688c;
|
||||
+ ctx->state[6] = 0x1f83d9ab;
|
||||
+ ctx->state[7] = 0x5be0cd19;
|
||||
+}
|
||||
+
|
||||
+static void sha256_update(struct sha256_ctx *ctx, const uint8_t *data, size_t len)
|
||||
+{
|
||||
+ uint32_t i;
|
||||
+
|
||||
+ for (i = 0; i < len; ++i) {
|
||||
+ ctx->data[ctx->datalen] = data[i];
|
||||
+ ctx->datalen++;
|
||||
+ if (ctx->datalen == 64) {
|
||||
+ /* 64 byte = 512 bit means the buffer ctx->data has
|
||||
+ * fully stored one chunk of message,
|
||||
+ * so do the sha256 hash map for the current chunk.
|
||||
+ */
|
||||
+ sha256_transform(ctx, ctx->data);
|
||||
+ ctx->bitlen += 512;
|
||||
+ ctx->datalen = 0;
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void sha256_final(struct sha256_ctx *ctx, uint8_t *hash)
|
||||
+{
|
||||
+ uint32_t i;
|
||||
+
|
||||
+ i = ctx->datalen;
|
||||
+
|
||||
+ /* Pad whatever data is left in the buffer. */
|
||||
+ if (ctx->datalen < 56) {
|
||||
+ ctx->data[i++] = 0x80; /* pad 10000000 = 0x80 */
|
||||
+ while (i < 56)
|
||||
+ ctx->data[i++] = 0x00;
|
||||
+ } else {
|
||||
+ ctx->data[i++] = 0x80;
|
||||
+ while (i < 64)
|
||||
+ ctx->data[i++] = 0x00;
|
||||
+ sha256_transform(ctx, ctx->data);
|
||||
+ memset(ctx->data, 0, 56);
|
||||
+ }
|
||||
+
|
||||
+ /* Append to the padding the total message's length in bits and transform. */
|
||||
+ ctx->bitlen += ctx->datalen * 8;
|
||||
+ ctx->data[63] = ctx->bitlen;
|
||||
+ ctx->data[62] = ctx->bitlen >> 8;
|
||||
+ ctx->data[61] = ctx->bitlen >> 16;
|
||||
+ ctx->data[60] = ctx->bitlen >> 24;
|
||||
+ ctx->data[59] = ctx->bitlen >> 32;
|
||||
+ ctx->data[58] = ctx->bitlen >> 40;
|
||||
+ ctx->data[57] = ctx->bitlen >> 48;
|
||||
+ ctx->data[56] = ctx->bitlen >> 56;
|
||||
+ sha256_transform(ctx, ctx->data);
|
||||
+
|
||||
+ /* copying the final state to the output hash(use big endian). */
|
||||
+ for (i = 0; i < 4; ++i) {
|
||||
+ hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ hash[i + 20] = (ctx->state[5] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ hash[i + 24] = (ctx->state[6] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ hash[i + 28] = (ctx->state[7] >> (24 - i * 8)) & 0x000000ff;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output)
|
||||
+{
|
||||
+ struct sha256_ctx ctx;
|
||||
+
|
||||
+ sha256_init(&ctx);
|
||||
+ sha256_update(&ctx, plaintext, psize);
|
||||
+ sha256_final(&ctx, output);
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/drivers/misc/sunxi-addr/sunxi-addr.c b/drivers/misc/sunxi-addr/sunxi-addr.c
|
||||
new file mode 100644
|
||||
index 000000000..a812e4e82
|
||||
--- /dev/null
|
||||
+++ b/drivers/misc/sunxi-addr/sunxi-addr.c
|
||||
@@ -0,0 +1,358 @@
|
||||
+/*
|
||||
+ * The driver of SUNXI NET MAC ADDR Manager.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 Allwinner.
|
||||
+ *
|
||||
+ * This file is licensed under the terms of the GNU General Public
|
||||
+ * License version 2. This program is licensed "as is" without any
|
||||
+ * warranty of any kind, whether express or implied.
|
||||
+ */
|
||||
+#define DEBUG
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/miscdevice.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#define ADDR_MGT_DBG(fmt, arg...) printk(KERN_DEBUG "[ADDR_MGT] %s: " fmt "\n",\
|
||||
+ __func__, ## arg)
|
||||
+#define ADDR_MGT_ERR(fmt, arg...) printk(KERN_ERR "[ADDR_MGT] %s: " fmt "\n",\
|
||||
+ __func__, ## arg)
|
||||
+
|
||||
+#define MODULE_CUR_VERSION "v1.0.9"
|
||||
+
|
||||
+#define MATCH_STR_LEN 20
|
||||
+#define ADDR_VAL_LEN 6
|
||||
+#define ADDR_STR_LEN 18
|
||||
+#define ID_LEN 16
|
||||
+#define HASH_LEN 32
|
||||
+
|
||||
+#define TYPE_ANY 0
|
||||
+#define TYPE_BURN 1
|
||||
+#define TYPE_IDGEN 2
|
||||
+#define TYPE_USER 3
|
||||
+#define TYPE_RAND 4
|
||||
+
|
||||
+#define ADDR_FMT_STR 0
|
||||
+#define ADDR_FMT_VAL 1
|
||||
+
|
||||
+#define IS_TYPE_INVALID(x) ((x < TYPE_ANY) || (x > TYPE_RAND))
|
||||
+
|
||||
+#define ADDR_CLASS_ATTR_ADD(name) \
|
||||
+static ssize_t addr_##name##_show(struct class *class, \
|
||||
+ struct class_attribute *attr, char *buffer) \
|
||||
+{ \
|
||||
+ char addr[ADDR_STR_LEN]; \
|
||||
+ if (IS_TYPE_INVALID(get_addr_by_name(ADDR_FMT_STR, addr, #name))) \
|
||||
+ return 0; \
|
||||
+ return sprintf(buffer, "%.17s\n", addr); \
|
||||
+} \
|
||||
+static ssize_t addr_##name##_store(struct class *class, \
|
||||
+ struct class_attribute *attr, \
|
||||
+ const char *buffer, size_t count) \
|
||||
+{ \
|
||||
+ if (count != ADDR_STR_LEN) { \
|
||||
+ ADDR_MGT_ERR("Length wrong."); \
|
||||
+ return -EINVAL; \
|
||||
+ } \
|
||||
+ set_addr_by_name(TYPE_USER, ADDR_FMT_STR, buffer, #name); \
|
||||
+ return count; \
|
||||
+} \
|
||||
+static CLASS_ATTR_RW(addr_##name);
|
||||
+
|
||||
+struct addr_mgt_info {
|
||||
+ unsigned int type_def;
|
||||
+ unsigned int type_cur;
|
||||
+ unsigned int flag;
|
||||
+ char *addr;
|
||||
+ char *name;
|
||||
+};
|
||||
+
|
||||
+static struct addr_mgt_info info[] = {
|
||||
+ {TYPE_ANY, TYPE_ANY, 1, NULL, "wifi"},
|
||||
+ {TYPE_ANY, TYPE_ANY, 0, NULL, "bt" },
|
||||
+ {TYPE_ANY, TYPE_ANY, 1, NULL, "eth" },
|
||||
+};
|
||||
+
|
||||
+extern int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output);
|
||||
+extern int sunxi_get_soc_chipid(unsigned char *chipid);
|
||||
+
|
||||
+static int addr_parse(int fmt, const char *addr, int check)
|
||||
+{
|
||||
+ char val_buf[ADDR_VAL_LEN];
|
||||
+ char cmp_buf[ADDR_VAL_LEN];
|
||||
+ int ret = ADDR_VAL_LEN;
|
||||
+
|
||||
+ if (fmt == ADDR_FMT_STR)
|
||||
+ ret = sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
|
||||
+ &val_buf[0], &val_buf[1], &val_buf[2],
|
||||
+ &val_buf[3], &val_buf[4], &val_buf[5]);
|
||||
+ else
|
||||
+ memcpy(val_buf, addr, ADDR_VAL_LEN);
|
||||
+
|
||||
+ if (ret != ADDR_VAL_LEN)
|
||||
+ return -1;
|
||||
+
|
||||
+ if (check && (val_buf[0] & 0x3))
|
||||
+ return -1;
|
||||
+
|
||||
+ memset(cmp_buf, 0x00, ADDR_VAL_LEN);
|
||||
+ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
|
||||
+ return -1;
|
||||
+
|
||||
+ memset(cmp_buf, 0xFF, ADDR_VAL_LEN);
|
||||
+ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
|
||||
+ return -1;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct addr_mgt_info *addr_find_by_name(char *name)
|
||||
+{
|
||||
+ int i = 0;
|
||||
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
|
||||
+ if (strcmp(info[i].name, name) == 0)
|
||||
+ return &info[i];
|
||||
+ }
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+static int get_addr_by_name(int fmt, char *addr, char *name)
|
||||
+{
|
||||
+ struct addr_mgt_info *t;
|
||||
+
|
||||
+ t = addr_find_by_name(name);
|
||||
+ if (t == NULL) {
|
||||
+ ADDR_MGT_ERR("can't find addr named: %s", name);
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ if (IS_TYPE_INVALID(t->type_cur)) {
|
||||
+ ADDR_MGT_ERR("addr type invalid");
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ if (addr_parse(ADDR_FMT_VAL, t->addr, t->flag)) {
|
||||
+ ADDR_MGT_ERR("addr parse fail(%s)", t->addr);
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ if (fmt == ADDR_FMT_STR)
|
||||
+ sprintf(addr, "%02X:%02X:%02X:%02X:%02X:%02X",
|
||||
+ t->addr[0], t->addr[1], t->addr[2],
|
||||
+ t->addr[3], t->addr[4], t->addr[5]);
|
||||
+ else
|
||||
+ memcpy(addr, t->addr, ADDR_VAL_LEN);
|
||||
+
|
||||
+ return t->type_cur;
|
||||
+}
|
||||
+
|
||||
+static int set_addr_by_name(int type, int fmt, const char *addr, char *name)
|
||||
+{
|
||||
+ struct addr_mgt_info *t;
|
||||
+
|
||||
+ t = addr_find_by_name(name);
|
||||
+ if (t == NULL) {
|
||||
+ ADDR_MGT_ERR("can't find addr named: %s", name);
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ if (addr_parse(fmt, addr, t->flag)) {
|
||||
+ ADDR_MGT_ERR("addr parse fail(%s)", addr);
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ t->type_cur = type;
|
||||
+ if (fmt == ADDR_FMT_STR)
|
||||
+ sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
|
||||
+ &t->addr[0], &t->addr[1], &t->addr[2],
|
||||
+ &t->addr[3], &t->addr[4], &t->addr[5]);
|
||||
+ else
|
||||
+ memcpy(t->addr, addr, ADDR_VAL_LEN);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int get_custom_mac_address(int fmt, char *name, char *addr)
|
||||
+{
|
||||
+ return get_addr_by_name(fmt, addr, name);
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(get_custom_mac_address);
|
||||
+
|
||||
+static int addr_factory(struct device_node *np,
|
||||
+ int idx, int type, char *mac, char *name)
|
||||
+{
|
||||
+ int ret, i;
|
||||
+ char match[MATCH_STR_LEN];
|
||||
+ const char *p;
|
||||
+ char id[ID_LEN], hash[HASH_LEN], cmp_buf[ID_LEN];
|
||||
+ struct timespec64 curtime;
|
||||
+
|
||||
+ switch (type) {
|
||||
+ case TYPE_BURN:
|
||||
+ sprintf(match, "addr_%s", name);
|
||||
+ ret = of_property_read_string_index(np, match, 0, &p);
|
||||
+ if (ret)
|
||||
+ return -1;
|
||||
+
|
||||
+ ret = sscanf(p, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
|
||||
+ &mac[0], &mac[1], &mac[2],
|
||||
+ &mac[3], &mac[4], &mac[5]);
|
||||
+
|
||||
+ if (ret != ADDR_VAL_LEN)
|
||||
+ return -1;
|
||||
+ break;
|
||||
+ case TYPE_IDGEN:
|
||||
+ if (idx > HASH_LEN / ADDR_VAL_LEN - 1)
|
||||
+ return -1;
|
||||
+ if (sunxi_get_soc_chipid(id))
|
||||
+ return -1;
|
||||
+ memset(cmp_buf, 0x00, ID_LEN);
|
||||
+ if (memcmp(id, cmp_buf, ID_LEN) == 0)
|
||||
+ return -1;
|
||||
+ if (hmac_sha256(id, ID_LEN, hash))
|
||||
+ return -1;
|
||||
+ memcpy(mac, &hash[idx * ADDR_VAL_LEN], ADDR_VAL_LEN);
|
||||
+ break;
|
||||
+ case TYPE_RAND:
|
||||
+ for (i = 0; i < ADDR_VAL_LEN; i++) {
|
||||
+ ktime_get_real_ts64(&curtime);
|
||||
+ mac[i] = (char)curtime.tv_nsec;
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ ADDR_MGT_ERR("unsupport type: %d", type);
|
||||
+ return -1;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int addr_init(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ int type, i, j;
|
||||
+ char match[MATCH_STR_LEN];
|
||||
+ char addr[ADDR_VAL_LEN];
|
||||
+ int type_tab[] = {TYPE_BURN, TYPE_IDGEN, TYPE_RAND};
|
||||
+
|
||||
+ /* init addr type and value */
|
||||
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
|
||||
+ sprintf(match, "type_addr_%s", info[i].name);
|
||||
+ if (of_property_read_u32(np, match, &type)) {
|
||||
+ ADDR_MGT_DBG("Failed to get type_def_%s, use default: %d",
|
||||
+ info[i].name, info[i].type_def);
|
||||
+ } else {
|
||||
+ info[i].type_def = type;
|
||||
+ info[i].type_cur = type;
|
||||
+ }
|
||||
+
|
||||
+ if (IS_TYPE_INVALID(info[i].type_def))
|
||||
+ return -1;
|
||||
+ if (info[i].type_def != TYPE_ANY) {
|
||||
+ if (addr_factory(np, i, info[i].type_def, addr, info[i].name))
|
||||
+ return -1;
|
||||
+ } else {
|
||||
+ for (j = 0; j < ARRAY_SIZE(type_tab); j++) {
|
||||
+ if (!addr_factory(np, i, type_tab[j], addr, info[i].name)) {
|
||||
+ info[i].type_cur = type_tab[j];
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (info[i].flag)
|
||||
+ addr[0] &= 0xFC;
|
||||
+
|
||||
+ if (addr_parse(ADDR_FMT_VAL, addr, info[i].flag))
|
||||
+ return -1;
|
||||
+ else {
|
||||
+ info[i].addr = devm_kzalloc(&pdev->dev, ADDR_VAL_LEN, GFP_KERNEL);
|
||||
+ memcpy(info[i].addr, addr, ADDR_VAL_LEN);
|
||||
+ }
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static ssize_t summary_show(struct class *class,
|
||||
+ struct class_attribute *attr, char *buffer)
|
||||
+{
|
||||
+ int i = 0, ret = 0;
|
||||
+
|
||||
+ ret += sprintf(&buffer[ret], "name cfg cur address\n");
|
||||
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
|
||||
+ ret += sprintf(&buffer[ret],
|
||||
+ "%4s %d %d %02X:%02X:%02X:%02X:%02X:%02X\n",
|
||||
+ info[i].name, info[i].type_def, info[i].type_cur,
|
||||
+ info[i].addr[0], info[i].addr[1], info[i].addr[2],
|
||||
+ info[i].addr[3], info[i].addr[4], info[i].addr[5]);
|
||||
+ }
|
||||
+ return ret;
|
||||
+}
|
||||
+static CLASS_ATTR_RO(summary);
|
||||
+
|
||||
+ADDR_CLASS_ATTR_ADD(wifi);
|
||||
+ADDR_CLASS_ATTR_ADD(bt);
|
||||
+ADDR_CLASS_ATTR_ADD(eth);
|
||||
+
|
||||
+static struct attribute *addr_class_attrs[] = {
|
||||
+ &class_attr_summary.attr,
|
||||
+ &class_attr_addr_wifi.attr,
|
||||
+ &class_attr_addr_bt.attr,
|
||||
+ &class_attr_addr_eth.attr,
|
||||
+ NULL
|
||||
+};
|
||||
+ATTRIBUTE_GROUPS(addr_class);
|
||||
+
|
||||
+static struct class addr_class = {
|
||||
+ .name = "addr_mgt",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .class_groups = addr_class_groups,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id addr_mgt_ids[] = {
|
||||
+ { .compatible = "allwinner,sunxi-addr_mgt" },
|
||||
+ { /* Sentinel */ }
|
||||
+};
|
||||
+
|
||||
+static int addr_mgt_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ int status;
|
||||
+
|
||||
+ ADDR_MGT_DBG("module version: %s", MODULE_CUR_VERSION);
|
||||
+ status = class_register(&addr_class);
|
||||
+ if (status < 0) {
|
||||
+ ADDR_MGT_ERR("class register error, status: %d.", status);
|
||||
+ return -1;
|
||||
+ }
|
||||
+
|
||||
+ if (addr_init(pdev)) {
|
||||
+ ADDR_MGT_ERR("failed to init addr.");
|
||||
+ class_unregister(&addr_class);
|
||||
+ return -1;
|
||||
+ }
|
||||
+ ADDR_MGT_DBG("success.");
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int addr_mgt_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ class_unregister(&addr_class);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver addr_mgt_driver = {
|
||||
+ .probe = addr_mgt_probe,
|
||||
+ .remove = addr_mgt_remove,
|
||||
+ .driver = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .name = "sunxi-addr-mgt",
|
||||
+ .of_match_table = addr_mgt_ids,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver_probe(addr_mgt_driver, addr_mgt_probe);
|
||||
+
|
||||
+MODULE_AUTHOR("Allwinnertech");
|
||||
+MODULE_DESCRIPTION("Network MAC Addess Manager");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--
|
||||
2.25.1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,28 @@
|
||||
From 70a0c21f9bc1eed754cce584fe382883dc412db0 Mon Sep 17 00:00:00 2001
|
||||
From: afaulkner420 <afaulkner420@gmail.com>
|
||||
Date: Fri, 25 Mar 2022 20:31:26 +0000
|
||||
Subject: [PATCH 08/11] uwe5622: bluetooth: Fix firmware init fail
|
||||
|
||||
---
|
||||
net/bluetooth/hci_core.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
|
||||
index c67390367..b2ee9b6a8 100644
|
||||
--- a/net/bluetooth/hci_core.c
|
||||
+++ b/net/bluetooth/hci_core.c
|
||||
@@ -932,7 +932,11 @@ static int __hci_init(struct hci_dev *hdev)
|
||||
|
||||
err = __hci_req_sync(hdev, hci_init3_req, 0, HCI_INIT_TIMEOUT, NULL);
|
||||
if (err < 0)
|
||||
+#if defined(CONFIG_RK_WIFI_DEVICE_UWE5621) || defined(CONFIG_AW_WIFI_DEVICE_UWE5622)
|
||||
+ ;
|
||||
+#else
|
||||
return err;
|
||||
+#endif
|
||||
|
||||
err = __hci_req_sync(hdev, hci_init4_req, 0, HCI_INIT_TIMEOUT, NULL);
|
||||
if (err < 0)
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,45 @@
|
||||
From bb564341bb6c64003abbf24fd5d5ef254060b040 Mon Sep 17 00:00:00 2001
|
||||
From: Patryk Biel <patryk.biel.external@trumpf.com>
|
||||
Date: Thu, 19 Jan 2023 10:46:28 +0100
|
||||
Subject: [PATCH] Fix incldue path for unisocwcn
|
||||
|
||||
---
|
||||
drivers/net/wireless/uwe5622/Makefile | 4 +++-
|
||||
drivers/net/wireless/uwe5622/unisocwcn/Makefile | 6 +++---
|
||||
2 files changed, 6 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/net/wireless/uwe5622/Makefile b/drivers/net/wireless/uwe5622/Makefile
|
||||
index 313ea5123..e9a398584 100644
|
||||
--- a/drivers/net/wireless/uwe5622/Makefile
|
||||
+++ b/drivers/net/wireless/uwe5622/Makefile
|
||||
@@ -2,7 +2,9 @@ obj-$(CONFIG_AW_WIFI_DEVICE_UWE5622) += unisocwcn/
|
||||
obj-$(CONFIG_WLAN_UWE5622) += unisocwifi/
|
||||
obj-$(CONFIG_TTY_OVERY_SDIO) += tty-sdio/
|
||||
|
||||
-UNISOCWCN_DIR := $(shell cd $(src)/unisocwcn/ && /bin/pwd)
|
||||
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
|
||||
+UNISOCWCN_DIR := $(dir $(mkfile_path))/unisocwcn/
|
||||
+
|
||||
UNISOC_BSP_INCLUDE := $(UNISOCWCN_DIR)/include
|
||||
export UNISOC_BSP_INCLUDE
|
||||
|
||||
diff --git a/drivers/net/wireless/uwe5622/unisocwcn/Makefile b/drivers/net/wireless/uwe5622/unisocwcn/Makefile
|
||||
index b62652f63..ae6e1e25a 100644
|
||||
--- a/drivers/net/wireless/uwe5622/unisocwcn/Makefile
|
||||
+++ b/drivers/net/wireless/uwe5622/unisocwcn/Makefile
|
||||
@@ -119,9 +119,9 @@ ccflags-y += -DCONFIG_WCN_UTILS
|
||||
|
||||
#### include path ######
|
||||
ccflags-y += -I$(src)/../tty-sdio
|
||||
-ccflags-y += -I$(src)/include/
|
||||
-ccflags-y += -I$(src)/platform/
|
||||
-ccflags-y += -I$(src)/platform/rf/
|
||||
+ccflags-y += -I$(srctree)/$(src)/include/
|
||||
+ccflags-y += -I$(srctree)/$(src)/platform/
|
||||
+ccflags-y += -I$(srctree)/$(src)/platform/rf/
|
||||
|
||||
#### add cflag for Customer ######
|
||||
### ---------- Hisilicon start ---------- ###
|
||||
--
|
||||
2.34.1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -5,3 +5,19 @@ DESCRIPTION = "Mainline Longterm Linux kernel"
|
||||
LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46"
|
||||
|
||||
SRC_URI[sha256sum] = "0a1a5ae2f30eb2b38215e59077f045aabd7f4e2857a881482f02ea48186105d8"
|
||||
|
||||
|
||||
# # orangepi-zero-2 support added only for 5.15 kernel so add it to this recipe not to inc file
|
||||
SRC_URI:append:orange-pi-zero2 = " \
|
||||
file://defconfig \
|
||||
file://0001-dts-add-h616-and-orangepizero2.patch \
|
||||
file://0002-drv-add-dump_reg-and-sunxi-sysinfo-drivers.patch \
|
||||
file://0003-drv-add-sunxi_get_soc_chipid-and-sunxi_get_serial.patch \
|
||||
file://0004-dts-add-sunxi-info-device-tree-node.patch \
|
||||
file://0005-dts-add-addr_mgt-device-tree-node.patch \
|
||||
file://0006-drv-modem-power-Power-manager-for-modems.patch \
|
||||
file://0007-drv-add-sunxi-addr-driver-used-to-fix-uwe5622-bluetooth-.patch \
|
||||
file://0008-drv-wireless-add-uwe5622-driver.patch \
|
||||
file://0009-drv-uwe5622-bluetooth-fix-firmware-init-fail.patch \
|
||||
file://0010-drv-fix-incldue-path-for-unisocwcn.patch \
|
||||
"
|
||||
|
||||
BIN
recipes-kernel/uwe5622-firmware/files/wcnmodem.bin
Normal file
BIN
recipes-kernel/uwe5622-firmware/files/wcnmodem.bin
Normal file
Binary file not shown.
177
recipes-kernel/uwe5622-firmware/files/wifi_2355b001_1ant.ini
Normal file
177
recipes-kernel/uwe5622-firmware/files/wifi_2355b001_1ant.ini
Normal file
@ -0,0 +1,177 @@
|
||||
[Section 1: Version]
|
||||
Major = 2
|
||||
Minor = 2
|
||||
|
||||
[Section 2: Board Config]
|
||||
Calib_Bypass = 11758
|
||||
TxChain_Mask = 2
|
||||
RxChain_Mask = 2
|
||||
|
||||
[Section 3: Board Config TPC]
|
||||
DPD_LUT_idx = 0x33,0x33,0x0,0x11,0x22,0x33,0x33,0x33
|
||||
TPC_Goal_Chain0 = 0,0,0,0,0,0,0,0
|
||||
TPC_Goal_Chain1 = 159,167,162,152,159,167,162,152
|
||||
|
||||
[Section 4: TPC-LUT]
|
||||
Chain0_LUT_0 = 6,0,40,0
|
||||
Chain0_LUT_1 = 6,1,24,0
|
||||
Chain0_LUT_2 = 6,2,8,0
|
||||
Chain0_LUT_3 = 10,2,0,0
|
||||
Chain0_LUT_4 = 14,2,0,0
|
||||
Chain0_LUT_5 = 18,2,0,0
|
||||
Chain0_LUT_6 = 22,2,0,0
|
||||
Chain0_LUT_7 = 26,2,0,0
|
||||
Chain1_LUT_0 = 6,0,40,0
|
||||
Chain1_LUT_1 = 6,1,24,0
|
||||
Chain1_LUT_2 = 6,2,8,0
|
||||
Chain1_LUT_3 = 10,2,0,0
|
||||
Chain1_LUT_4 = 14,2,0,0
|
||||
Chain1_LUT_5 = 18,2,0,0
|
||||
Chain1_LUT_6 = 22,2,0,0
|
||||
Chain1_LUT_7 = 26,2,0,0
|
||||
|
||||
[Section 5: Board Config Frequency Compensation]
|
||||
2G_Channel_Chain0 = 6,6,6,6,7,7,7,7,7,7,7,7,7,7
|
||||
2G_Channel_Chain1 = 6,6,6,6,7,7,7,7,7,7,7,7,7,7
|
||||
5G_Channel_Chain0 = 11,11,11,11,9,9,9,9,10,10,10,10,10,10,10,10,10,10,10,10,9,9,9,9,9
|
||||
5G_Channel_Chain1 = 11,11,11,11,9,9,9,9,10,10,10,10,10,10,10,10,10,10,10,10,9,9,9,9,9
|
||||
|
||||
[Section 6: Rate To Power with BW 20M]
|
||||
11b_Power = 20,20,20,20
|
||||
11ag_Power = 28,32,36,44,28,32,36,48
|
||||
11n_Power = 34,38,38,40,40,44,44,48,32,36,36,40,40,44,44,54,48
|
||||
11ac_Power = 32,36,36,40,40,44,44,48,50,66,32,36,36,40,40,44,44,48,50,66
|
||||
|
||||
[Section 7: Power Backoff]
|
||||
Green_WIFI_offset = 0
|
||||
HT40_Power_offset = 0
|
||||
VHT40_Power_offset = 0
|
||||
VHT80_Power_offset = 0
|
||||
SAR_Power_offset = 0
|
||||
Mean_Power_offset = 36
|
||||
|
||||
[Section 8: Reg Domain]
|
||||
reg_domain1 = 0x00000001
|
||||
reg_domain2 = 0x00000002
|
||||
|
||||
[Section 9: Band Edge Power offset (MKK, FCC, ETSI)]
|
||||
BW20M = 3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41
|
||||
BW40M = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21
|
||||
BW80M = 6,5,4,3,2,1
|
||||
|
||||
[Section 10: TX Scale]
|
||||
Chain0_1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
|
||||
Chain1_1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
|
||||
Chain0_2 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,17
|
||||
Chain1_2 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,17
|
||||
Chain0_3 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,18
|
||||
Chain1_3 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,18
|
||||
Chain0_4 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,19
|
||||
Chain1_4 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,19
|
||||
Chain0_5 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,20
|
||||
Chain1_5 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,20
|
||||
Chain0_6 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,21
|
||||
Chain1_6 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,21
|
||||
Chain0_7 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22
|
||||
Chain1_7 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22
|
||||
Chain0_8 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,23
|
||||
Chain1_8 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,23
|
||||
Chain0_9 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,24
|
||||
Chain1_9 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,24
|
||||
Chain0_10 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,25
|
||||
Chain1_10 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,25
|
||||
Chain0_11 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,26
|
||||
Chain1_11 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,26
|
||||
Chain0_12 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,27
|
||||
Chain1_12 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,27
|
||||
Chain0_13 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,28
|
||||
Chain1_13 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,28
|
||||
Chain0_14 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,29
|
||||
Chain1_14 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,29
|
||||
Chain0_36 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,30
|
||||
Chain1_36 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,30
|
||||
Chain0_40 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,31
|
||||
Chain1_40 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,31
|
||||
Chain0_44 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,32
|
||||
Chain1_44 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,32
|
||||
Chain0_48 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,33
|
||||
Chain1_48 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,33
|
||||
Chain0_52 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,34
|
||||
Chain1_52 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,34
|
||||
Chain0_56 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,35
|
||||
Chain1_56 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,35
|
||||
Chain0_60 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,36
|
||||
Chain1_60 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,36
|
||||
Chain0_64 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,37
|
||||
Chain1_64 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,37
|
||||
Chain0_100 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,38
|
||||
Chain1_100 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,38
|
||||
Chain0_104 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,39
|
||||
Chain1_104 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,39
|
||||
Chain0_108 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,40
|
||||
Chain1_108 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,40
|
||||
Chain0_112 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,41
|
||||
Chain1_112 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,41
|
||||
Chain0_116 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,42
|
||||
Chain1_116 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,42
|
||||
Chain0_120 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,43
|
||||
Chain1_120 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,43
|
||||
Chain0_124 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,44
|
||||
Chain1_124 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,44
|
||||
Chain0_128 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,45
|
||||
Chain1_128 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,45
|
||||
Chain0_132 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,46
|
||||
Chain1_132 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,46
|
||||
Chain0_136 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,47
|
||||
Chain1_136 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,47
|
||||
Chain0_140 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,48
|
||||
Chain1_140 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,48
|
||||
Chain0_144 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,49
|
||||
Chain1_144 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,49
|
||||
Chain0_149 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,50
|
||||
Chain1_149 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,50
|
||||
Chain0_153 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,51
|
||||
Chain1_153 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,51
|
||||
Chain0_157 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,52
|
||||
Chain1_157 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,52
|
||||
Chain0_161 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,53
|
||||
Chain1_161 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,53
|
||||
Chain0_165 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,54
|
||||
Chain1_165 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,54
|
||||
|
||||
[Section 11: misc]
|
||||
DFS_switch = 1
|
||||
power_save_switch = 2
|
||||
ex-Fem_and_ex-LNA_param_setup = 3
|
||||
rssi_report_diff = 4
|
||||
|
||||
[Section 12: debug reg]
|
||||
address = 0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0x10,0x11,0x12,0x13,0x14,0x15,0x16
|
||||
value = 0x16,0x17,0x18,0x19,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x30,0x31
|
||||
|
||||
[Section 13: coex_config]
|
||||
bt_performance_cfg0 = 0x01010101
|
||||
bt_performance_cfg1 = 0x01000000
|
||||
wifi_performance_cfg0 = 0x01050A01
|
||||
wifi_performance_cfg2 = 0x00000000
|
||||
strategy_cfg0 = 0x01010100
|
||||
strategy_cfg1 = 0x03000000
|
||||
strategy_cfg2 = 0x08020000
|
||||
compatibility_cfg0 = 0x04040000
|
||||
compatibility_cfg1 = 0x0
|
||||
ant_cfg0 = 0x0
|
||||
ant_cfg1 = 0x0
|
||||
isolation_cfg0 = 0x0505
|
||||
isolation_cfg1 = 0x0
|
||||
reserved_cfg0 = 0x0
|
||||
reserved_cfg1 = 0x0
|
||||
reserved_cfg2 = 0x0
|
||||
reserved_cfg3 = 0x0
|
||||
reserved_cfg4 = 0x0
|
||||
reserved_cfg5 = 0x0
|
||||
reserved_cfg6 = 0x0
|
||||
reserved_cfg7 = 0x0
|
||||
|
||||
[Section 14: rf_tlv_config]
|
||||
rf_config = 0xAA,0x55,0x00,0xFF,0x8,0xA,0x0,0x5,0x0,0x0,0x0,0x0,0x0,0x0
|
||||
|
||||
22
recipes-kernel/uwe5622-firmware/uwe5622-firmware.bb
Normal file
22
recipes-kernel/uwe5622-firmware/uwe5622-firmware.bb
Normal file
@ -0,0 +1,22 @@
|
||||
DESCRIPTION = "UWE5622 Wifi firmware"
|
||||
LICENSE = "CC0-1.0"
|
||||
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/${LICENSE};md5=0ceb3372c9595f0a8067e55da801e4a1"
|
||||
|
||||
S = "${WORKDIR}"
|
||||
|
||||
COMPATIBLE_MACHINE = "orange-pi-zero2"
|
||||
|
||||
SRC_URI:append = " \
|
||||
file://wcnmodem.bin \
|
||||
file://wifi_2355b001_1ant.ini \
|
||||
"
|
||||
|
||||
do_install() {
|
||||
install -d ${D}${base_libdir}/firmware
|
||||
install -m 0644 ${S}/wcnmodem.bin ${D}${base_libdir}/firmware/wcnmodem.bin
|
||||
install -m 0644 ${S}/wifi_2355b001_1ant.ini ${D}${base_libdir}/firmware/wifi_2355b001_1ant.ini
|
||||
}
|
||||
|
||||
FILES:${PN} = "${base_libdir}/*"
|
||||
|
||||
PACKAGES = "${PN}"
|
||||
Loading…
Reference in New Issue
Block a user