mirror of
https://github.com/patjak/facetimehd.git
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148 lines
4.1 KiB
C
148 lines
4.1 KiB
C
/*
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* Broadcom PCIe 1570 webcam driver
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* Some of the register defines are taken from the crystalhd driver
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*
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* Copyright (C) 2014 Patrik Jakobsson (patrik.r.jakobsson@gmail.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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*/
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#ifndef _BCWC_REG_H
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#define _BCWC_REG_H
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/* S2 IO reg */
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#define S2_PCIE_LINK_D000 0xd000
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#define S2_PCIE_LINK_D120 0xd120
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#define S2_PCIE_LINK_D124 0xd124
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#define S2_PCIE_LINK_D128 0xd128
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#define S2_PCIE_LINK_D12C 0xd12c
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/* These are written to 0x203 before DDR soc init */
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#define S2_DDR_REG_1100 0x1100
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#define S2_DDR_REG_1104 0x1104
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#define S2_DDR_REG_1108 0x1108
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#define S2_DDR_REG_110C 0x110c
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#define S2_DDR_REG_1110 0x1110
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#define S2_DDR_REG_1114 0x1114
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#define S2_DDR_REG_1118 0x1118
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#define S2_DDR_REG_111C 0x111c
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#define S2_PLL_STATUS_04 0x04
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#define S2_PLL_REFCLK (1 << 3) /* 1 = 25MHz, 0 = 24MHz */
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#define S2_PLL_STATUS_0C 0x0c /* Register is called CMU_R_PLL_STS_MEMADDR */
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#define S2_PLL_STATUS_LOCKED (1 << 15) /* 1 = PLL locked, 0 = PLL not locked */
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#define S2_PLL_STATUS_A8 0xa8
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#define S2_PLL_BYPASS (1 << 0) /* 1 = bypass, 0 = non-bypass */
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#define S2_PLL_CTRL_14 0x0014
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#define S2_PLL_CTRL_20 0x0020
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#define S2_PLL_CTRL_24 0x0024
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#define S2_PLL_CTRL_2C 0x002c
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#define S2_PLL_CTRL_9C 0x009c
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#define S2_PLL_CTRL_100 0x0100
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#define S2_PLL_CTRL_510 0x0510
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/* Probably DDR PHY PLL registers */
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#define S2_DDR_2004 0x2004
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#define S2_DDR_2008 0x2008
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#define S2_DDR_2014 0x2014
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#define S2_DDR_STATUS_2018 0x2018
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#define S2_DDR_STATUS_BUSY (1 << 0)
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#define S2_DDR_20A0 0x20a0
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#define S2_DDR_20A4 0x20a4
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#define S2_DDR_20A8 0x20a8
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#define S2_DDR_20B0 0x20b0
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#define S2_20F8 0x20f8
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#define S2_DDR_2118 0x2118
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#define S2_2430 0x2430
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#define S2_2434 0x2434
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#define S2_2438 0x2438
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#define S2_DDR_PLL_STATUS_241C 0x241c
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#define S2_DDR_PLL_STATUS_241C_LOCKED 0x0400
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#define S2_DDR_PLL_STATUS_2444 0x2444
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#define S2_DDR_PLL_STATUS_2444_LOCKED 0x2000
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#define DDR_PHY_REG_BASE 0x2800
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#define DDR_PHY_NUM_REGS 127 /* Found in AppleCamIn::Start() */
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/* DDR40 */
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#define S2_DDR40_PHY_BASE 0x2800
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#define S2_DDR40_PHY_PLL_STATUS 0x2810
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#define S2_DDR40_PHY_PLL_STATUS_LOCKED (1 << 0)
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#define S2_DDR40_PHY_PLL_CFG 0x2814
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#define S2_DDR40_PHY_PLL_DIV 0x281c
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#define S2_DDR40_AUX_CTL 0x2820
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#define S2_DDR40_PHY_VDL_OVR_COARSE 0x2830
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#define S2_DDR40_PHY_VDL_OVR_FINE 0x2834
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#define S2_DDR40_PHY_ZQ_PVT_COMP_CTL 0x283c
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#define S2_DDR40_PHY_DRV_PAD_CTL 0x2840
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#define S2_DDR40_PHY_VDL_CTL 0x2848
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#define S2_DDR40_PHY_VDL_STATUS 0x284c
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#define S2_DDR40_PHY_DQ_CALIB_STATUS 0x2850
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#define S2_DDR40_PHY_VDL_CHAN_STATUS 0x2854
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#define S2_DDR40_PHY_VTT_CTL 0x285c
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#define S2_DDR40_PHY_VTT_STATUS 0x2860
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#define S2_DDR40_PHY_VTT_CONNECTIONS 0x2864
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#define S2_DDR40_PHY_VTT_OVERRIDE 0x2868
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#define S2_DDR40_STRAP_CTL 0x28b0
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#define S2_DDR40_STRAP_CTL_2 0x28b4
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#define S2_DDR40_STRAP_STATUS 0x28b8
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#define S2_DDR40_NUM_BYTE_LANES 2
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#define S2_DDR40_BYTE_LANE_SIZE 0xa0
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#define S2_DDR40_RDEN_BYTE 0x2a00
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#define S2_DDR40_2A08 0x2a08
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#define S2_DDR40_2A0C 0x2a0c
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#define S2_DDR40_2A38 0x2a38
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#define S2_DDR40_RDEN_BYTE0 0x2a74
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#define S2_DDR40_2AA8 0x2aa8
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#define S2_DDR40_2AAC 0x2aac
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#define S2_DDR40_RDEN_BYTE1 0x2b14
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#define S2_DDR40_RD_DATA_DLY_FIFO 0x2b60
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#define S2_DDR40_2B64 0x2b64
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#define S2_DDR40_TIMING_STATUS 0x2b90
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#define S2_DDR40_TIMING_CTL 0x2b94
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#define S2_2BA4 0x2ba4
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#define S2_2BA8 0x2ba8
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#define S2_2BA0 0x2ba0
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#define S2_2BAC 0x2bac
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#define S2_3200 0x3200
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#define S2_3204 0x3204
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#define S2_3208 0x3208
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/* On iomem with pointer at 0x0ff0 (Bar 4: 1MB) */
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#define IRQ_IPC_NUM_CHAN 0xc3000
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#define IRQ_IPC_QUEUE_SIZE 0xc3004
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#define IRQ_REG_08 0xc3008
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#define IRQ_FW_HEAP_SIZE 0xc300c
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#define IRQ_REG_10 0xc3010
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#define IRQ_REG_14 0xc3014
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#define IRQ_REG_18 0xc3018
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#define IRQ_REG_1C 0xc301c
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#define IRQ_REG_40004 0x40004
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#define IRQ_REG_40008 0x40008
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#define IRQ_REG_41000 0x41000
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#define IRQ_REG_41024 0x41024
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#define IRQ_REG_RANGE_START 0x0128
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#define IRQ_REG_RANGE_END 0x0220
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#endif
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