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bcwc_pcie: Minor DDR PHY changes

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Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
Patrik Jakobsson
2015-06-14 22:42:38 +02:00
parent f048239d5e
commit d8195d5b00
1 changed files with 5 additions and 3 deletions
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8
bcwc_ddr.c
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@@ -414,7 +414,7 @@ static int bcwc_ddr_generic_shmoo_rd_dqs(struct bcwc_private *dev_priv,
}
setting++;
tmp = (setting & 63) | 0x30100;
tmp = (setting & 0x3f) | 0x30100;
/* Byte 0 */
BCWC_S2_REG_WRITE(tmp, S2_DDR40_2A08);
@@ -424,7 +424,9 @@ static int bcwc_ddr_generic_shmoo_rd_dqs(struct bcwc_private *dev_priv,
BCWC_S2_REG_WRITE(tmp, S2_DDR40_2AA8);
BCWC_S2_REG_WRITE(tmp, S2_DDR40_2AAC);
fail = setting > 62;
if (setting > 62)
fail = 1;
offset = S2_DDR40_RDEN_BYTE0;
/* Write byte lane settings */
@@ -436,7 +438,7 @@ static int bcwc_ddr_generic_shmoo_rd_dqs(struct bcwc_private *dev_priv,
BCWC_S2_REG_WRITE((bytes[i] & 0x3f) | 0x30100, offset);
offset += 160;
offset += 0xa0;
}
}